AD7893
–9–
REV. E
The AD7893 counts the serial clock edges to know which bit
from the output register should be placed on the SDATA out-
put. To ensure that the part does not lose synchronization, the
serial clock counter is reset on the falling edge of the
CONVST
input, provided the SCLR line is low. The user should ensure
that a falling edge on the
CONVST input does not occur while
a serial data read operation is in progress.
MICROPROCESSOR/MICROCONTROLLER INTERFACE
The AD7893 provides a two-wire serial interface that can be
used for connection to the serial ports of DSP processors and
microcontrollers. Figures 6 through 9 show the AD7893 inter-
faced to a number of different microcontrollers and DSP pro-
cessors. The AD7893 accepts an external serial clock and, as a
result, in all interfaces shown here, the processor/controller is
configured as the master, providing the serial clock with the
AD7893 configured as the slave in the system.
AD7893-8051 Interface
Figure 6 shows an interface between the AD7893 and the
8XC51 microcontroller. The 8XC51 is configured for its Mode
0 serial interface mode. The diagram shows the simplest form of
the interface where the AD7893 is the only part connected to
the serial port of the 8XC51 and, therefore, no decoding of the
serial read operations is required. It also makes no provisions for
monitoring when conversion is complete on the AD7893.
Either of these two tasks can readily be accomplished with minor
modifications to the interface. To chip select the AD7893 in
systems where more than one device is connected to the 8XC51’s
serial port, a port bit configured as an output from one of the
8XC51’s parallel ports can be used to gate on or off the serial
clock to the AD7893. A simple AND function on this port bit
and the serial clock from the 8XC51 will provide this function.
The port bit should be high to select the AD7893 and low when
it is not selected.
To monitor the conversion time on the AD7893, a scheme such
as previously outlined with
CONVST can be used. This can be
implemented in two ways. One is to connect the
CONVST line
to another parallel port bit that is configured as an input. This
port bit can then be polled to determine when conversion is
complete. An alternative is to use an interrupt driven system, in
which case the
CONVST line should be connected to the INT1
input of the 8XC51.
The serial clock rate from the 8XC51 is limited to significantly
less than the allowable input serial clock frequency with which
the AD7893 can operate. As a result, the time to read data from
the part will actually be longer than the conversion time of the
part. This means that the AD7893 cannot run at its maximum
throughput rate when used with the 8XC51.
AD7893-68HC11 Interface
An interface circuit between the AD7893 and the 68HC11
microcontroller is shown in Figure 7. For the interface shown,
the 68HC11 SPI port is used, and the 68HC11 is configured in
its single-chip mode. The 68HC11 is configured in the master
mode with its CPOL bit set to a logic zero and its CPHA bit set
to a logic one. As with the previous interface, the diagram shows
the simplest form of the interface where the AD7893 is the only
part connected to the serial port of the 68HC11 and, therefore,
no decoding of the serial read operations is required. It also
makes no provisions for monitoring when conversion is com-
plete on the AD7893.
Once again, either of these two tasks can readily be accom-
plished with minor modifications to the interface. To chip select
the AD7893 in systems where more than one device is con-
nected to the 68HC11’s serial port, a port bit, configured as an
output from one of the 68HC11’s parallel ports, can be used to
gate on or off the serial clock to the AD7893. A simple AND
function on this port bit and the serial clock from the 68HC11
will provide this function. The port bit should be high to select
the AD7893 and low when it is not selected.
To monitor the conversion time on the AD7893, a scheme such
as outlined in the previous interface with
CONVST can be
used. This can be implemented in two ways. One is to connect
the
CONVST line to another parallel port bit that is configured
as an input. This port bit can then be polled to determine when
conversion is complete. An alternative is to use an interrupt
driven system, in which case the
CONVST line should be con-
nected to the IRQ input of the 68HC11.
The serial clock rate from the 68HC11 is limited to significantly
less than the allowable input serial clock frequency with which
the AD7893 can operate. As a result, the time to read data from
the part will actually be longer than the conversion time of the
part. This means that the AD7893 cannot run at its maximum
throughput rate when used with the 68HC11.
AD7893
SDATA
SCLK
8XC51
P3.0
P3.1
Figure 6. AD7893 to 8XC51 Interface
AD7893
SDATA
SCLK
68HC11
SCK
MISO
Figure 7. AD7893 to 68HC11 Interface
