AD7893ARZ-5 Datasheet AD7893BNZ-10, AD7893ARZ-5, AD7893BRZ-2 | P7-P9

AD7893

REV. E

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CONVERTER DETAILS

The AD7893 is a fast, 12-bit single supply A/D converter. It

provides the user with signal scaling (AD7893-10), track/hold,

A/D converter and serial interface logic functions on a single

chip. The A/D converter section of the AD7893 consists of a

conventional successive-approximation converter based on an

R-2R ladder structure. The signal scaling on the AD7893-10,

AD7893-5 and AD7893-3 allows the part to handle ±10 V, 0 V

to +5 V and ±2.5 V input signals, respectively, while operating

from a single +5 V supply. The AD7893-2 accepts an analog in-

put range of 0 V to +2.5 V. The part requires an external +2.5 V

reference. The reference input to the part is buffered on-chip.

A major advantage of the AD7893 is that it provides all of the

above functions in an 8-pin package, either 8-pin mini-DIP or

SOIC. This offers the user considerable space saving advantages

over alternative solutions. The AD7893 typically consumes only

25 mW, making it ideal for battery-powered applications.

Conversion is initiated on the AD7893 by pulsing the

CONVST

input. On the rising edge of

CONVST, the on-chip track/hold

goes from track-to-hold mode and the conversion sequence is

started. The conversion clock for the part is generated internally

using a laser-trimmed clock oscillator circuit. Conversion time

for the AD7893 is 6 µs, and the track/hold acquisition time is

1.5 µs. To obtain optimum performance from the part, the read

operation should not occur during the conversion or during

600 ns prior to the next conversion. This allows the part to op-

erate at throughput rates up to 117 kHz and to achieve data

sheet specifications. The part can operate at higher throughput

rates (up to 133 kHz) with slightly degraded performance (see

Timing and Control section).

CIRCUIT DESCRIPTION

Analog Input Section

The AD7893 is offered as four part types: the AD7893-10,

which handles a ±10 V input voltage range; the AD7893-3,

which handles a ±2.5 V input voltage range; the AD7893-5,

which handles a 0 V to +5 V input range; and the AD7893-2,

which handles a 0 V to +2.5 V input voltage range.

Figure 2 shows the analog input section for the AD7893-10,

AD7893-5 and AD7893-3. The analog input range of the

AD7893-10 is ±10 V into an input resistance of typically 33 kΩ.

The analog input range of the AD7893-3 is ±2.5 V into an input

resistance of typically 12 kΩ. The input range on the AD7893-5 is

0 V to +5 V into an input resistance of typically 11 kΩ. This in-

put is benign with no dynamic charging currents, as the resistor

stage is followed by a high input impedance stage of the track/hold

AGND

AD7893-10/AD7893-5

REF IN

TRACK/

HOLD

TO ADC

REFERENCE

CIRCUITRY

TO INTERNAL

COMPARATOR

Figure 2. AD7893-10/AD7893-3/AD7893-5 Analog Input

Structure

amplifier. For the AD7893-10, R1 = 30 kΩ; R2 = 7.5 kΩ and

R3 = 10 kΩ. For the AD7893-3, R1 = R2 = 6.5 kΩ, and R3

is open circuit. For the AD7893-5, R1 and R3 = 5 kΩ while

R2 is open-circuit.

For the AD7893-10 and AD7893-3, the designed code transi-

tions occur on successive integer LSB values (i.e., 1 LSB, 2 LSBs,

3 LSBs . . .). Output coding is twos complement binary with

1 LSB = FS/4096. The ideal input/output transfer function for

the AD7893-10 and AD7893-3 is shown in Table I.

Table I. Ideal Input/Output Code Table for the AD7893-10/

AD7893-3

Digital Output

Analog Input

Code Transition

+FSR/2 – 1 LSB

011 . . . 110 to 011 . . . 111

+FSR/2 – 2 LSBs 011 . . . 101 to 011 . . . 110

+FSR/2 – 3 LSBs 011 . . . 100 to 011 . . . 101

AGND + 1 LSB 000 . . . 000 to 000 . . . 001

AGND 111 . . . 111 to 000 . . . 000

AGND – 1 LSB 111 . . . 110 to 111 . . . 111

–FSR/2 + 3 LSBs 100 . . . 010 to 100 . . . 011

–FSR/2 + 2 LSBs 100 . . . 001 to 100 . . . 010

–FSR/2 + 1 LSB 100 . . . 000 to 100 . . . 001

NOTES

FSR is full-scale range and is 20 V (AD7893-10) and = 5 V (AD7893-3) with

REF IN = +2.5 V.

1 LSB = FSR/4096 = 4.883 mV (AD7893-10) and 1.22 mV (AD7893-3) with

REF IN = +2.5 V.

For the AD7893-5, the designed code transitions occur again on

successive integer LSB values. Output coding is straight (natural)

binary with 1 LSB = FS/4096 = 5 V/4096 = 1.22 mV. The ideal

input/output transfer function for the AD7893-5 is shown in

Table II.

The analog input section for the AD7893-2 contains no biasing

resistors, and the V

pin drives the input directly to the track/

hold amplifier. The analog input range is 0 V to +2.5 V into a

high impedance stage, with an input current of less than

500 nA. This input is benign, with no dynamic charging cur-

rents. Once again, the designed code transitions occur on suc-

cessive integer LSB values. Output coding is straight (natural)

binary with 1 LSB = FS/4096 = 2.5 V/4096 = 0.61 mV. Table

II also shows the ideal input/output transfer function for the

AD7893-2.

Table II. Ideal Input/Output Code Table for

AD7893-2/AD7893-5

Digital Output

Analog Input

Code Transition

+FSR – 1 LSB

111 . . . 110 to 111 . . . 111

+FSR – 2 LSB 111 . . . 101 to 111 . . . 110

+FSR – 3 LSB 111 . . . 100 to 111 . . . 101

AGND + 3 LSB 000 . . . 010 to 000 . . . 011

AGND + 2 LSB 000 . . . 001 to 000 . . . 010

AGND + 1 LSB 000 . . . 000 to 000 . . . 001

NOTES

FSR is Full-Scale Range and is 5 V for AD7893-5 and 2.5 V for AD7893-2

with REF IN = +2.5 V.

1 LSB = FSR/4096 and is 1.22 mV for AD7893-5 and 0.61 mV for AD7893-2

with REF IN = +2.5 V.

AD7893

–7–

REV. E

Track/Hold Section

The track/hold amplifier on the analog input of the AD7893

allows the ADC to accurately convert an input sine wave of full-

scale amplitude to 12-bit accuracy. The input bandwidth of the

track/hold is greater than the Nyquist rate of the ADC, even

when the ADC is operated at its maximum throughput rate of

117 kHz (i.e., the track/hold can handle input frequencies in

excess of 58 kHz).

The track/hold amplifier acquires an input signal to 12-bit accu-

racy in less than 1.5 µs. The operation of the track/hold is essen-

tially transparent to the user. The track/hold amplifier goes from

its tracking mode to its hold mode at the start of conversion

(i.e., the rising edge of

CONVST). The aperture time for the

track/hold (i.e., the delay time between the external

CONVST

signal and the track/hold actually going into hold) is typically

15 ns. At the end of conversion (6 µs after the rising edge of

CONVST) the part returns to its tracking mode. The acquisi-

tion time of the track/hold amplifier begins at this point.

Reference Input

The reference input to the AD7893 is a buffered on-chip with a

maximum reference input current of 1 µA. The part is specified

with a +2.5 V reference input voltage. Errors in the reference

source will result in gain errors in the AD7893’s transfer func-

tion and will add to the specified full-scale errors on the part.

On the AD7893-10 it will also result in an offset error injected

in the attenuator stage. Suitable reference sources for the

AD7893 include the AD780 and AD680 precision +2.5 V

references.

Timing and Control Section

Figure 3 shows the timing and control sequence required to ob-

tain optimum performance from the AD7893. In the sequence

shown, conversion is initiated on the rising edge of

CONVST,

and new data from this conversion is available in the output reg-

ister of the AD7893 6 µs later. Once the read operation has

taken place, a further 600 ns should be allowed before the next

rising edge of

CONVST to optimize the settling of the track/

hold amplifier before the next conversion is initiated. With the

serial clock frequency at its maximum of 8.33 MHz, the achiev-

able throughput rate for the part is 6 µs (conversion time) plus

1.92 µs (read time) plus 0.6 µs (acquisition time). This results in

a minimum throughput time of 8.52 µs (equivalent to a through-

put rate of 117 kHz).

The read operation consists of sixteen serial clock pulses to the

output shift register of the AD7893. After sixteen serial clock

pulses the shift register is reset and the SDATA line is three-

stated. If there are more serial clock pulses after the sixteenth

clock, the shift register will be moved on past its reset state;

however, the shift register will be reset again on the falling edge

of the

CONVST signal to ensure that the part returns to a

known state every conversion cycle. As a result, a read operation

from the output register should not straddle across the falling

edge of

CONVST as the output shift register will be reset in the

middle of the read operation, and the data read back into the

microprocessor will appear invalid.

The throughput rate of the part can be increased by reading

data during conversion. If the data is read during conversion,

a throughput time of 6 µs (conversion time) plus 1.5 µs is

achieved. This minimum throughput time of 7.5 µs is achieved

with a slight reduction in performance from the AD7893. The

signal to (noise + distortion) number is likely to degrade by ap-

proximately 1.5 dB while the code flicker from the part will also

increase (see AD7893 PERFORMANCE section).

Because the AD7893 is provided in an 8-pin package to mini-

mize board space, the number of pins available for interfacing is

very limited. As a result, no status signal is provided from the

AD7893 to indicate when conversion is complete. In many

applications, this will not be a problem as the data can be read

from the AD7893 during conversion or after conversion; how-

ever, applications that want to achieve optimum performance

from the AD7893 will have to ensure that the data read does not

occur during conversion or during 600 ns prior to the rising

edge of

CONVST. This can be achieved in two ways. The first

is to ensure in software that the read operation is not initiated

until 6 µs after the rising edge of

CONVST. This will only be

possible if the software knows when the

CONVST command is

issued. The second scheme would be to use the

CONVST sig-

nal as both the conversion start signal and an interrupt signal.

The simplest way to do this would be to generate a square wave

signal for

CONVST with high and low times of 6 µs (see Figure

4). Conversion is initiated on the rising edge of

CONVST. The

falling edge of

CONVST occurs 6 µs later and can be used as ei-

ther an active low or falling, edge-triggered interrupt signal to

tell the processor to read the data from the AD7893. Provided

that the read operation is completed 600 ns before the rising

edge of

CONVST, the AD7893 will operate to specification.

CONVST

SCLK

CONVERSION IS INITIATED

AND TRACK/HOLD GOES

INTO HOLD

CONVERSION ENDS

6µs LATER

SERIAL READ

OPERATION

OUTPUT SERIAL

SHIFT REGISTER IS

RESET

600ns MIN

CONVERT

READ OPERATION

SHOULD END 600ns

PRIOR TO NEXT

RISING EDGE OF

CONVST

Figure 3. Timing Sequence for Optimum Performance from the AD7893

AD7893

REV. E

–8–

This scheme limits the throughput rate to 12 µs minimum; how-

ever, depending on the response time of the microprocessor to

the interrupt signal and the time taken by the processor to read

the data, this may be the fastest the system could have operated.

In any case, the

CONVST signal does not have to have a 50:50

duty cycle. This can be tailored to optimize the throughput rate

of the part for a given system.

Alternatively, the

CONVST signal can be used as a normal narrow

pulse width. The rising edge of

CONVST can be used as an active

high or rising edge-triggered interrupt. A software delay of 6 µs can

then be implemented before data is read from the part.

Serial Interface

The serial interface to the AD7893 consists of just two wires, a

serial clock input (SCLK) and the serial data output (SDATA).

This allows for an easy to use interface to most microcontrollers,

DSP processors and shift registers.

Figure 5 shows the timing diagram for the read operation to the

AD7893. The serial clock input (SCLK) provides the clock

source for the serial interface. Serial data is clocked out from the

SDATA line on the rising edge of this clock and is valid on the

falling edge of SCLK. Sixteen clock pulses must be provided to

the part to access to full conversion result. The AD7893 pro-

vides four leading zeros followed by the 12-bit conversion result

starting with the MSB (DB11). The last data bit to be clocked

out on the final rising clock edge is the LSB (DB0). On the six-

teenth falling edge of SCLK, the SDATA line is disabled (three-

stated). After this last bit has been clocked out, the SCLK input

should return low and remain low until the next serial data read

operation. If there are extra clock pulses after the sixteenth

clock, the AD7893 will start over again with outputting data

from its output register, and the data bus will no longer be

three-stated even when the clock stops. Provided that the serial

clock has stopped before the next falling edge of

CONVST, the

AD7893 will continue to operate correctly with the output shift

CONVST; however,

the SCLK line must be low when

CONVST goes low in order

to reset the output shift register correctly.

The serial clock input does not have to be continuous during the

serial read operation. The sixteen bits of data (four leading zeros

and 12 bit conversion result) can be read from the AD7893 in a

number of bytes; however, the SCLR input must remain low be-

tween the two bytes.

Normally, the output register is updated at the end of conver-

sion. If a serial read from the output register is in progress when

conversion is complete; however, the updating of the output

when the serial read is completed. If the serial read has not been

completed before the next falling edge of

CONVST, the output

CONVST, and

the output shift register count is reset. In applications where the

data read has been started and not completed before the falling

edge of

CONVST, the user must provide a CONVST pulse

width of greater than 1.5 µs to ensure correct setup of the AD7893

before the next conversion is initiated. In applications where the

output update takes place either at the end of conversion or at

the end of a serial read that is completed 1.5 µs before the rising

edge of

CONVST, the normal pulse width of 50 ns minimum

applies to

CONVST.

CONVST

SCLK

CONVERSION IS INITIATED

AND TRACK/HOLD GOES

INTO HOLD

CONVST INDICATES

TO µP THAT

CONVERSION IS

COMPLETE

CONVERT

SERIAL READ

OPERATION

µP INT SERVICE

OR POLLING

ROUTINE

600ns MIN

READ OPERATION

SHOULD END 600ns

PRIOR TO NEXT

RISING EDGE OF

CONVST

Figure 4.

CONVST

Used as Status Signal

SDATA (O)

SCLK (I)

FOUR LEADING ZEROS

DB11 DB10

THREE-STATE

DB0

Figure 5. Data Read Operation

P1-P3 P4-P6 P7-P9 P10-P12 P13-P13

AD7893ARZ-5

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Analog to Digital Converters - ADC Bipolar Input SGL Spply 12B Serial 6uS

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