XC2C512-10FT256C Datasheet XC2C512-10FT256C, XC2C512-10FG324I, XC2C512-10FG324C | P1-P3

DS096 (v3.2) March 8, 2007 www.xilinx.com 1

Product Specification

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Features

• Optimized for 1.8V systems

- As fast as 7.1 ns pin-to-pin delays

- As low as 14 μA quiescent current

• Industry’s best 0.18 micron CMOS CPLD

- Optimized architecture for effective logic synthesis

- Multi-voltage I/O operation — 1.5V to 3.3V

• Available in multiple package options

- 208-pin PQFP with 173 user I/O

- 256-ball FT (1.0mm) BGA with 212 user I/O

- 324-ball FG (1.0mm) BGA with 270 user I/O

- Pb-free available for all packages

• Advanced system features

- Fastest in system programming

· 1.8V ISP using IEEE 1532 (JTAG) interface

- IEEE1149.1 JTAG Boundary Scan Test

- Optional Schmitt-trigger input (per pin)

- Unsurpassed low power management

· DataGATE enable signal control

- Four separate I/O banks

- RealDigital 100% CMOS product term generation

- Flexible clocking modes

· Optional DualEDGE triggered registers

· Clock divider (divide by 2,4,6,8,10,12,14,16)

· CoolCLOCK

- Global signal options with macrocell control

· Multiple global clocks with phase selection per

macrocell

· Multiple global output enables

· Global set/reset

- Advanced design security

- PLA architecture

· Superior pinout retention

· 100% product term routability across function

block

- Open-drain output option for Wired-OR and LED

drive

- Optional bus-hold, 3-state or weak pullup on

selected I/O pins

- Optional configurable grounds on unused I/Os

- Mixed I/O voltages compatible with 1.5V, 1.8V,

2.5V, and 3.3V logic levels

· SSTL2-1, SSTL3-1, and HSTL-1 I/O compatibility

- Hot Pluggable

Refer to the CoolRunner™-II family data sheet for architec-

ture description.

Description

The CoolRunner-II 512-macrocell device is designed for

both high performance and low power applications. This

lends power savings to high-end communication equipment

and high speed to battery operated devices. Due to the low

power stand-by and dynamic operation, overall system reli-

ability is improved

This device consists of thirty two Function Blocks inter-con-

nected by a low power Advanced Interconnect Matrix (AIM).

The AIM feeds 40 true and complement inputs to each

Function Block. The Function Blocks consist of a 40 by 56

P-term PLA and 16 macrocells which contain numerous

configuration bits that allow for combinational or registered

modes of operation.

Additionally, these registers can be globally reset or preset

and configured as a D or T flip-flop or as a D latch. There

are also multiple clock signals, both global and local product

term types, configured on a per macrocell basis. Output pin

configurations include slew rate limit, bus hold, pull-up,

open drain and programmable grounds. A Schmitt-trigger

input is available on a per input pin basis. In addition to stor-

ing macrocell output states, the macrocell registers may be

configured as "direct input" registers to store signals directly

from input pins.

Clocking is available on a global or Function Block basis.

Three global clocks are available for all Function Blocks as

a synchronous clock source. Macrocell registers can be

individually configured to power up to the zero or one state.

A global set/reset control line is also available to asynchro-

nously set or reset selected registers during operation.

Additional local clock, synchronous clock-enable, asynchro-

nous set/reset and output enable signals can be formed

using product terms on a per-macrocell or per-Function

Block basis.

A DualEDGE flip-flop feature is also available on a per mac-

rocell basis. This feature allows high performance synchro-

nous operation based on lower frequency clocking to help

reduce the total power consumption of the device.

Circuitry has also been included to divide one externally

supplied global clock (GCK2) by eight different selections.

This yields divide by even and odd clock frequencies.

The use of the clock divide (division by 2) and DualEDGE

flip-flop gives the resultant CoolCLOCK feature.

DataGATE is a method to selectively disable inputs of the

CPLD that are not of interest during certain points in time.

XC2C512 CoolRunner-II CPLD

DS096 (v3.2) March 8, 2007

Product Specification

XC2C512 CoolRunner-II CPLD

2 www.xilinx.com DS096 (v3.2) March 8, 2007

Product Specification

By mapping a signal to the DataGATE function, lower power

can be achieved due to reduction in signal switching.

Another feature that eases voltage translation is I/O bank-

ing. Four I/O banks are available on the CoolRunner-II 512

macrocell device that permits easy interfacing to 3.3V, 2.5V,

1.8V, and 1.5V devices.

The CoolRunner-II 512 macrocell CPLD is I/O compatible

with various JEDEC I/O standards (see Table 1). This

device is also 1.5V I/O compatible with the use of

Schmitt-trigger inputs.

RealDigital Design Technology

Xilinx CoolRunner-II CPLDs are fabricated on a 0.18 micron

process technology which is derived from leading edge

FPGA product development. CoolRunner-II CPLDs employ

RealDigital, a design technique that makes use of CMOS

technology in both the fabrication and design methodology.

RealDigital design technology employs a cascade of CMOS

gates to implement sum of products instead of traditional

sense amplifier methodology. Due to this technology, Xilinx

CoolRunner-II CPLDs achieve both high-performance and

low power operation.

Supported I/O Standards

The CoolRunner-II 512 macrocell features LVCMOS,

LVTTL, SSTL, and HSTL I/O implementations. See Table 1

for I/O standard voltages. The LVTTL I/O standard is a gen-

eral purpose EIA/JEDEC standard for 3.3V applications that

use an LVTTL input buffer and Push-Pull output buffer. The

LVCMOS standard is used in 3.3V, 2.5V, 1.8V applications.

Both HSTL and SSTL I/O standards make use of a V

REF

for JEDEC compliance. CoolRunner-II CPLDs are also 1.5V

I/O compatible with the use of Schmitt-trigger inputs.

Table 1: I/O Standards for XC2C512

(1)

IOSTANDARD

Attribute

Output

CCIO

Input

CCIO

Input

REF

Board

Termination

Voltage V

LVTTL 3.3 3.3 N/A N/A

LVCMOS33 3.3 3.3 N/A N/A

LVCMOS25 2.5 2.5 N/A N/A

LVCMOS18 1.8 1.8 N/A N/A

LVCMOS15

(2)

1.5 1.5 N/A N/A

HSTL_1 1.5 1.5 0.75 0.75

SSTL2_1 2.5 2.5 1.25 1.25

SSTL3_1 3.3 3.3 1.5 1.5

(1) For information on Vref pins, see XAPP399.

(2) LVCMOS15 requires Schmitt-trigger inputs.

Figure 1: I

vs Frequency

Table 2: I

vs Frequency (LVCMOS 1.8V T

= 25°C)

(1)

Frequency (MHz)

0 20 40 60 80 100 120 140 160 180

Typical I

(mA) 0.025 17.22 34.37 52.04 69.44 86.85 105.13 122.68 140.23 157.78

Notes:

1. 16-bit up/down, Resetable binary counter (one counter per function block).

Frequency (MHz)

DS096_01_030705

(mA)

100

150

200

1801601208020 14060 10040

250

XC2C512 CoolRunner-II CPLD

DS096 (v3.2) March 8, 2007 www.xilinx.com 3

Product Specification

Recommended Operating Conditions

DC Electrical Characteristics

(Over Recommended Operating Conditions)

Absolute Maximum Ratings

Symbol Description Value Units

Supply voltage relative to ground –0.5 to 2.0 V

CCIO

Supply voltage for output drivers –0.5 to 4.0 V

JTAG

(2)

JTAG input voltage limits -0.5 to 4.0 V

CCAUX

JTAG input supply voltage -0.5 to 4.0 V

(1)

Input voltage relative to ground

(1)

–0.5 to 4.0 V

(1)

Voltage applied to 3-state output

(1)

–0.5 to 4.0 V

STG

(3)

Storage Temperature (ambient) –65 to +150 °C

Junction Temperature +150 °C

Notes:

1. Maximum DC undershoot below GND must be limited to either 0.5V or 10 mA, whichever is easiest to achieve. During transitions,

the device pins may undershoot to –2.0v or overshoot to +4.5V, provided this over or undershoot lasts less than 10 ns and with the

forcing current being limited to 200 mA.

2. Valid over commercial temperature range.

3. For soldering guidelines and thermal considerations, see the Device Packaging

information on the Xilinx website. For Pb free

packages, see XAPP427.

Symbol Parameter Min Max Units

Supply voltage for internal logic and

input buffers

Commercial T

= 0°C to +70°C 1.7 1.9 V

Industrial T

= –40°C to +85°C 1.7 1.9 V

CCIO

Supply voltage for output drivers @ 3.3V operation 3.0 3.6 V

Supply voltage for output drivers @ 2.5V operation 2.3 2.7 V

Supply voltage for output drivers @ 1.8V operation 1.7 1.9 V

Supply voltage for output drivers @ 1.5V operation 1.4 1.6 V

CCAUX

JTAG programming 1.7 3.6 V

Symbol Parameter Test Conditions Typical Max. Units

CCSB

Standby current Commercial V

= 1.9V, V

CCIO

= 3.6V 50 240 μA

CCSB

Standby current Industrial V

= 1.9V, V

CCIO

= 3.6V 150 400 μA

(1)

Dynamic current f = 1 MHz - 1 mA

f = 50 MHz - 55 mA

JTAG

JTAG input capacitance f = 1 MHz - 10 pF

CLK

Global clock input capacitance f = 1 MHz - 12 pF

I/O capacitance f = 1 MHz - 10 pF

(2)

Input leakage current V

= 0V or V

CCIO

to 3.9V - +/–1 μA

(2)

I/O High-Z leakage V

= 0V or V

CCIO

to 3.9V - +/–1 μA

Notes:

1. 16-bit up/down, Resetable binary counter (one counter per function block) tested at

= V

CCIO

= 1.9V.

2. See Quality and Reliability section of the CoolRunner-II family data sheet.

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XC2C512-10FT256C

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CPLD - Complex Programmable Logic Devices XC2C512-10FT256C

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