XC2C512 CoolRunner-II CPLD
DS096 (v3.2) March 8, 2007 www.xilinx.com 7
Product Specification
R
AC Electrical Characteristics Over Recommended Operating Conditions
Symbol Parameter
-7 -10
UnitsMin. Max. Min. Max.
T
PD1
Propagation delay (single p-term) - 7.1 - 9.2 ns
T
PD2
Propagation delay (OR array) - 7.5 - 10.0 ns
T
SUD
Direct input register set-up time 3.4 - 4.0 - ns
T
SU1
Setup time fast (single p-term) 2.6 - 3.1 - ns
T
SU2
Setup time (OR array) 3.0 - 3.9 - ns
T
H
Direct input register hold time 0 - 0 - ns
T
H
P-term hold time 0 - 0 - ns
T
CO
Clock to output - 5.8 - 7.9 ns
F
TOGGLE
(1)
Internal toggle rate - 250 - 166 MHz
F
SYSTEM1
(2)
Maximum system frequency - 179 - 128 MHz
F
SYSTEM2
(2)
Maximum system frequency - 167 - 116 MHz
F
EXT1
(3)
Maximum external frequency - 119 - 91 MHz
F
EXT2
(3)
Maximum external frequency - 114 - 85 MHz
T
PSUD
Direct input register p-term clock setup time 2.1 - 2.8 - ns
T
PSU1
P-term clock setup time (single p-term) 1.1 - 1.7 - ns
T
PSU2
P-term clock setup time (OR array) 1.5 - 2.5 - ns
T
PHD
Direct input register p-term clock hold time 0.1 - 0.4 - ns
T
PH
P-term clock hold 1.3 - 1.7 - ns
T
PCO
P-term clock to output - 7.3 - 9.3 ns
T
OE
/T
OD
Global OE to output enable/disable - 6.5 - 9.2 ns
T
POE
/T
POD
P-term OE to output enable/disable - 7.5 - 10.2 ns
T
MOE
/T
MOD
Macrocell driven OE to output enable/disable - 8.6 - 12.5 ns
T
PAO
P-term set/reset to output valid - 7.6 - 11.6 ns
T
AO
Global set/reset to output valid - 7.5 - 11.5 ns
T
SUEC
Register clock enable setup time 2.8 - 3.2 - ns
T
HEC
Register clock enable hold time 0 - 0 - ns
T
CW
Global clock pulse width High or Low 2.0 - 3.0 - ns
T
PCW
P-term pulse width High or Low 7.5 - 10.0 - ns
T
APRPW
Asynchronous preset/reset pulse width (High or Low) 7.5 - 10.0 - ns
T
DGSU
Set-up before DataGATE latch assertion 0.0 - 0.0 - ns
T
DGH
Hold to DataGATE latch assertion 4.0 - 6.0 - ns
T
DGR
DataGATE recovery to new data - 9.3 - 11.0 ns
T
DGW
DataGATE low pulse width 3.0 - 5.0 - ns
T
CDRSU
CDRST setup time before falling edge GCLK2 1.7 - 2.5 - ns
T
CDRH
Hold time CDRST after falling edge GCLK2 0 - 0 - ns
T
CONFIG
(4)
Configuration time - 400 - 400 μs
Notes:
1. F
TOGGLE
is the maximum clock frequency to which a T-Flip Flop can reliably toggle (see the CoolRunner-II family data sheet for more
information).
2. F
SYSTEM1
(1/T
CYCLE
) is the internal operating frequency for a device fully populated with 16-bit Resetable binary counter through
one p-term per macrocell while F
SYSTEM2
is through the OR array.
3. F
EXT1
(1/T
SU1
+T
CO
) is the maximum external frequency using one p-term while F
EXT2
is through the OR array
4. Typical configuration current during T
CONFIG
is approximately 15mA
