Functional Description 13 May 24, 2006
IDT82V3011 T1/E1/OC3 WAN PLL WITH SINGLE REFERENCE INPUT
2.6 DPLL BLOCK
As shown in Figure - 7, the DPLL Block consists of a Phase Detector,
a Limiter, a Loop Filter, a Digital Control Oscillator and Divider.
2.6.1 PHASE DETECTOR (PHD)
In the Normal mode, the Phase Detector compares the virtual
reference signal from the TIE Control Circuit with the feedback signal
from the Frequency Select Circuit, and outputs an error signal
corresponding to the phase difference. This error signal is sent to the
Limiter circuit for phase slope control.
In the Freerun or Holdover mode, the Frequency Select Circuit, the
Phase Detector and the Limiter are inactive, and the input reference
signal is not used.
2.6.2 LIMITER
The Limiter is used to limit the phase slope. It ensures that the
maximum output phase slope is limited to 5 ns per 125 µs for all input
transient conditions. This well meets the AT&T TR62411 and Telcordia
GR-1244-CORE specifications, which specify the maximum phase slope
of 7.6 ns per 125 µs and 81 ns per 1.326 ms respectively.
In the Normal mode, the Limiter receives the error signal from the
Phase Detector, limits the phase slope within 5 ns per 125 µs and sends
the limited signal to the Loop Filter.
In the Fast Lock mode, the Limiter is disabled, and the DPLL locks to
the input reference within 500 ms, which is much shorter than that in the
Normal mode.
2.6.3 LOOP FILTER
The Loop Filter ensures that the jitter transfer meets the ETS 300
011 and AT&T TR62411 requirements. It works similarly to a first order
low pass filter with 2.1 Hz cutoff frequency for the four valid input
frequencies (8 kHz, 1.544 MHz, 2.048 MHz or 19.44 MHz).
The output of the Loop Filter goes to the Digital Control Oscillator
directly or through the Fraction blocks, in which E1, T1 C6 and C19
signals are generated.
2.6.4 FRACTION BLOCK
By applying some algorithms to the incoming E1 signal, the
Fraction_C19, Fraction_C6 and Fraction_T1 blocks generate C19, C6
and T1 signals respectively.
2.6.5 DIGITAL CONTROL OSCILLATOR (DCO)
In the Normal mode, the DCO receives four limited and filtered
signals from Loop Filter or Fraction blocks. Based on the values of the
received signals, the DCO generates four digital outputs: 19.44 MHz,
25.248 MHz, 32.768 MHz and 24.704 MHz for C19, C6, E1 and T1
dividers respectively.
In the Holdover mode, the DCO is running at the same frequency as
that generated by storage techniques.
In the Freerun mode, the DCO is running at the same frequency as
that of the master clock.
2.6.6 LOCK INDICATOR
If the output frequency of the DPLL is identical to the input frequency,
and the input phase offset is small enough so that no slope limiting is
exhibited, the LOCK pin will be set high.
2.6.7 OUTPUT INTERFACE
The Output Interface uses three output signals from the DCO to
generate totally 9 types of clock signals and 7 types of framing signals.
All these output signals are synchronous to F8o.
The 32.768 MHz signal is used by the E1_divider to generate five
types of clock signals (C2o, C4o, C8o, C16o and C32o) with nominal
50% duty cycle and six types of framing signals (F0o, F8o, F16o, F32o,
RSP and TSP).
The 24.704 MHz signal is used by the T1_divider to generate two
types of T1 signals (C1.5o and C3o) with nominal 50% duty cycle.
The 25.248 MHz signal is used by the C6_divider to generate a C6o
signal with nominal 50% duty cycle.
The 19.44 MHz signal is sent to an APLL, which outputs a 155.52
MHz signal. The 155.52 MHz signal is used by the C19_divider to
generate 19.44 MHz clock signals (C19o, C19POS, C19NEG) with
nominal 50% duty cycle and a framing signal F19o.
Additionally, the IDT82V3011 provides an output clock (C2/C1.5) with
the frequency controlled by the frequency selection pins F_sel0 and
F_sel1. If the reference input is 8 kHz, 2.048 MHz or 19.44 MHz, the C2/
C1.5 pin will output a 2.048 MHz clock signal. If the reference input is
1.544 MHz, the C2/C1.5 pin will output a 1.544 MHz clock signal (see
Table - 3 for details). The electrical and timing characteristics of this
output (2.048 MHz or 1.544 MHz) is the same as that of C2o or C1.5o.
2.7 OSC
The IDT82V3011 can use a clock as the master timing source. In the
Freerun mode, the frequency tolerance of the clock outputs is identical
to the frequency tolerance of the source at the OSCi pin. For
applications not requiring an accurate Freerun mode, the tolerance of
the master timing source may be ±100 ppm. For applications requiring
an accurate Freerun mode, such as AT&T TR62411, the tolerance of the
master timing source must be no greater than ±32 ppm.
The desired capture range should be taken into consideration when
determining the accuracy of the master timing source. The sum of the
accuracy of the master timing source and the capture range of the
IDT82V3011 will always equal 230 ppm. For example, if the master
timing source is 100 ppm, the capture range will be 130 ppm.
2.7.1 CLOCK OSCILLATOR
When selecting a Clock Oscillator, numerous parameters must be
considered. This includes absolute frequency, frequency change over
temperature, output rise and fall times, output levels and duty cycle.
For applications requiring ±32 ppm clock accuracy, the following
clock oscillator module may be used.
Table - 3 C2/C1.5 Output Frequency Control
Frequency Selection Pins
Fref Input
Frequency
C2/C1.5 Output
Frequency
F_sel1 F_sel0
0 0 19.44 MHz 2.048 MHz
0 1 8 kHz 2.048 MHz
1 0 1.544 MHz 1.544 MHz
1 1 2.048 MHz 2.048 MHz
