82V3011PVG Datasheet 82V3011PVG, 82V3011PVG8 | P4-P6

Table Of Contents 4 May 24, 2006

7.10 8 kHz Input Jitter Tolerance.....................................................................................................................................................................23

7.11 1.544 MHz Input Jitter Tolerance ............................................................................................................................................................23

7.12 2.048 MHz Input Jitter Tolerance ............................................................................................................................................................24

7.13 19.44 MHz Input Jitter Tolerance ............................................................................................................................................................24

8 Timing Characteristics ....................................................................................................................................................................................26

8.1 Timing Parameter Measurement Voltage Levels ....................................................................................................................................26

8.2 Input/Output Timing .................................................................................................................................................................................26

9 Ordering Information .......................................................................................................................................................................................31

List of Figures 5 May 24, 2006

LIST OF FIGURES

Figure - 1 IDT82V3011 SSOP56 Package Pin Assignment ................................................................................................................................ 2

Figure - 2 State Control Circuit ............................................................................................................................................................................ 9

Figure - 3 State Control Diagram......................................................................................................................................................................... 9

Figure - 4 TIE Control Block Diagram................................................................................................................................................................ 11

Figure - 5 Reference Switch with TIE Control Block Enabled............................................................................................................................ 11

Figure - 6 Reference Switch with TIE Control Block Disabled........................................................................................................................... 12

Figure - 7 DPLL Block Diagram......................................................................................................................................................................... 12

Figure - 8 Clock Oscillator Circuit ...................................................................................................................................................................... 14

Figure - 9 Power-Up Reset Circuit..................................................................................................................................................................... 14

Figure - 10 IDT82V3011 Power Decoupling Scheme.......................................................................................................................................... 15

Figure - 11 Timing Parameter Measurement Voltage Levels .............................................................................................................................. 26

Figure - 12 Input to Output Timing (Normal Mode).............................................................................................................................................. 28

Figure - 13 Output Timing 1................................................................................................................................................................................. 29

Figure - 14 Output Timing 2................................................................................................................................................................................. 30

Figure - 15 Input Control Setup and Hold Timing ................................................................................................................................................ 30

List of Tables 6 May 24, 2006

LIST OF TABLES

Table - 1 Operating Modes Selection..................................................................................................................................................................9

Table - 2 Input Frequency Selection..................................................................................................................................................................10

Table - 3 C2/C1.5 Output Frequency Control....................................................................................................................................................13

P1-P3 P4-P6 P7-P9 P10-P12 P13-P15 P16-P18 P19-P21 P22-P24 P25-P27 P28-P30 P31-P31

82V3011PVG

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Buy 82V3011PVG

Manufacturer:

IDT

Description:

Clock Generators & Support Products T1/E1/OC3 WAN PLL

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New from this manufacturer.

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82V3011PVG

82V3011PVG

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