LTC6912
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Functional Description
The LTC6912-X is a small outline, wideband, inverting
two-channel amplifier with voltage gains that are indepen-
dently programmable. Each delivers a choice of eight
voltage gains, configurable through a 3-wire serial digital
interface, which accepts TTL or CMOS logic levels (See
Figure 5). Tables 1 and 2 list the nominal gains for the
LTC6912-1 and LTC6912-2 respectively. Gain control
within the amplifier occurs by switching resistors from a
matched array in or out of a closed-loop op amp circuit
using MOS analog switches (Figure 1). The bandwidths of
the individual amplifiers depend on gain setting. The
Typical Performance Characteristics section shows mea-
sured frequency responses.
Description of the 3-Wire SPI Interface
Gain control of each amplifier is independently program-
mable using the 3-wire SPI interface (see Figure 5). Logic
levels for the LTC6912 3-wire serial interface are TTL/
CMOS compatible. When CS/LD is low, the serial data on
D
IN
is shifted into an 8-bit shift-register on the rising edge
of the clock, with the MSB transferred first. Serial data on
D
OUT
is shifted out on the clock’s falling edge. A rising edge
on CS/LD will latch the shift-register’s contents into an 8-
bit D-latch and disable the clock internally on the IC. The
upper nibble of the D-latch (4 most significant bits),
configure the gain for the B-channel amplifier. The lower
nibble of the D-latch (4 least significant bits), configures
the gain for the A-channel amplifier. Tables 1 and 2 detail
the nominal gains and respective gain codes. Care must be
taken to ensure CLK is taken low before CS/LD is pulled
low to avoid an extra internal clock pulse to the input of the
8-bit shift-register (See Figure 5).
D
OUT
is active in all states, therefore D
OUT
cannot be
“wire-OR’d” to other SPI outputs.
An LTC6912 may be daisy-chained with other LTC6912s
or other devices having serial interfaces by connecting the
D
OUT
to the D
IN
of the next chip while CLK and CS/LD
remain common to all chips in the daisy chain. The serial
data is clocked to all the chips then the CS/LD signal is
pulled high to update all of them simultaneously. Figure 6
shows an example of two LTC6912s in a daisy chained SPI
Figure 5. Serial Digital Interface Block Diagram
CLK
CS/LD
SHDN
6912 F05
LOWER NIBBLE
UPPER NIBBLE
8-BIT LATCH
8-BIT
SHIFT-REGISTER
CHANNEL A CHANNEL B
Q0 Q1 Q2 Q3 Q4 Q5 Q6 Q7
D
OUT
LSB MSB
RESET
RESET
LE
D
IN
OUT A, OUT B: Analog Output. These pins are the output
of the A and B channel amplifiers respectively. Each
operational amplifier can swing rail-to-rail (V
+
to V
) as
specified in the Electrical Characteristics table. For best
performance, loading the output as lightly as possible will
minimize signal distortion and gain error. The Electrical
Characteristics table shows performance at output cur-
rents up to 10mA, and the current limits which occur when
the output is shorted midsupply at 2.7V and ±5V supplies.
Output current above 10mA is possible but current-limit-
ing circuitry will begin to affect amplifier performance at
approximately 20mA. Long-term operation above 20mA
output is not recommended. Do not exceed maximum
junction temperature of 150°C for a GN and 125°C for a
DFN package. The output will drive capacitive loads up to
50pF. Capacitances higher than 50pF should be isolated
by a series resistor (10 or higher).
LTC6912
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Figure 6. Two LTC6912s (Four PGAs) in Daisy Chain Configuration
1
2
3
4
5
6
7
8
16
15
14
13
12
11
10
9
LTC6912-X
0.1µF
0.1µF
V
+
V
DIGITAL GROUND PLANE
ANALOG GROUND PLANE
6912 F06
DGND
D
OUT
1
2
3
4
5
6
7
8
16
15
14
13
12
11
10
9
LTC6912-X
0.1µF
0.1µF
V
+
V
DGND
D
OUT
CS/LD
DATA
CLK
µP
SINGLE-POINT
SYSTEM GND
D15 D11 D10 D9 D8 D7 D3 D2 D1 D0
CLK
D
IN
CS/LD
SHDN
CS/LD
D
IN
SHDN
CS/LD
D
IN
configuration. It is recommended the serial interface sig-
nals should remain idle in between data transfers in order
to minimize digital noise coupling into the analog path.
Power On Reset
On the initial application of power, the power on reset
state of both amplifiers is low power software shutdown
(state = 8) (see Tables 1 and 2). In this state, both analog
amplifiers are disabled and have their inputs and outputs
opened. This will facilitate the application of using the
device as a 2:1 analog MUX, in that the amplifier’s outputs
may be wired-OR together and the LTC6912 can alter-
nately select between A and B channels. Care must be
taken if the outputs are wired-OR’d to ensure the software
shutdown state (state = 8) is always programmed in one
of the two channels.
Timing Constraints
Settling time in the CMOS gain-control logic is typically
several nanoseconds and is faster than the analog signal
path. When the amplifier gain changes, the limiting timing
is analog. As with any programmable-gain amplifier, each
gain change causes an output transient as the amplifier’s
output moves, with finite speed, toward a differently
scaled version of the input signal. The LTC6912-X analog
path settles with a characteristic time constant or time
scale, τ, that is roughly the standard value for a first order
band limited response:
τ = 0.35/f
–3dB
See the –3dB BW vs Gain Setting graph in the Typical
Performance Characteristics section.
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Offset Voltage vs Gain Setting
The electrical tables list DC offset (error), V
OS(OA)
, at the
inputs of the internal op amp (See Figure 1). The electrical
tables also show the resulting, gain dependent offset
voltage referred to the INA, or INB pins, V
OS(IN)
. The two
measures are related through the feedback/input resistor
ratio, which equals the nominal gain-magnitude setting,
|GAIN|:
V
OS(IN)
= (1 + 1/|GAIN|) V
OS(OA)
Offset voltages at any gain setting can be inferred from this
relationship. For example, an internal amplifier offset
V
OS(OA)
of 1mV will appear referred to the INA, INB pins as
2mV at a gain setting of 1, or 1.5mV at a gain setting of 2.
At high gains, V
OS(IN)
approaches V
OS(OA)
. (Offset voltage
is random and can have either polarity centered on 0V).
The MOS input circuitry of the internal op amp in Figure 1
draws negligible input currents (less than 10µA), so only
V
OS(OA)
and the GAIN affect the overall amplifier’s offset.
AC-Coupled Operation
Adding capacitors in series with the INA and INB pins
converts the LTC6912-X into a dual AC-coupled inverting
amplifier, suppressing the input signal’s DC level (and also
adding the additional benefit of reducing the offset voltage
from the LTC6912-X’s amplifier itself). No further compo-
nents are required because the input of the LTC6912-X
biases itself correctly when a series capacitor is added.
The INA and INB analog input pins connect internally to a
resistor whose nominal value varies between 10k and
1k depending on the version of LTC6912 used (see the
rightmost column of Tables 1 and 2). Therefore, the low
frequency cutoff will vary with capacitor and gain setting.
If, for example, a low frequency corner of 1kHz (or lower)
on the LTC6912-1 is desired, use a series capacitor of
0.16µF or larger. 0.16µF has a reactance of 1k at 1kHz,
giving a 1kHz lower –3dB frequency for gain settings of
10V/V through 100V/V. If the LTC6912-1 is operated at
lower gain settings with a 0.16µF capacitor, the higher
input resistance will reduce the lower corner frequency
down to 100Hz at a gain setting of 1V/V. These frequencies
scale inversely with the value of input capacitor used.
Note that operating the LTC6912 family in “zero” gain
mode (digital state 0000) open circuits both the INA and
INB pins and this demands some care if employed with a
series AC coupling input capacitor. When the chip enters
the zero gain mode, the opened INA or INB pin tends to
sample and freeze the voltage across the capacitor to the
value it held just before the zero gain state. This can place
the INA or INB pin at or near the DC potential of a supply
rail. (The INA or INB pin may also drift to a supply potential
in this state due to small leakage currents.) To prevent
driving the INA or INB pin outside the supply limit and
potentially damaging the chip, avoid AC input signals in
the zero gain state with an AC coupling capacitor. Also,
switching later to a non-zero gain value will cause a
transient pulse at the output of the LTC6912-1 (with a time
constant set by the capacitor value and the new LTC6912-1
input resistance value). This occurs because the INA and
INB pins return to the AGND potential forcing transient
current sourced by the amplifier output to charge the AC
coupling capacitor to its proper DC blocking value.
SNR and Dynamic Range
The term “dynamic range” is much used (and abused)
with signal paths. Signal-to-noise (SNR) is an unambigu-
ous comparison of signal and noise levels, measured in
the same way and under the same operating conditions. In
a variable gain amplifier, however, further characterization
is useful because both noise and maximum signal level in
the amplifier will vary with the gain setting, in general. In
the LTC6912-X, maximum output signal is independent of
gain (and is near the full power supply voltage, as detailed
in the swing sections of the Electrical Characteristics
table). The maximum input level falls with increasing gain,
and the input-referred noise falls as well (listed also in the
table). To summarize the useful signal range in such an
amplifier, we define dynamic range (DR) as the ratio of
maximum input (at unity gain) to minimum input-referred
noise (at maximum gain). This DR has a physical interpre-
tation as the range of signal levels that will experience an
SNR above unity V/V or 0dB. At a 10V total power supply,
DR in the LTC6912-X (gains 0V/V to 100V/V), the DR is
typically 115dB (the ratio of 9.9 V
P-P
, or 3.5V
RMS
, maxi-
mum input to the 6.3µV
RMS
high gain input noise). The

LTC6912CDE-1#TRPBF

Mfr. #:
Manufacturer:
Analog Devices Inc.
Description:
Special Purpose Amplifiers 2x Progmable Gain Amps w/ Serial Dig Int
Lifecycle:
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