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24LCS22A-I/P

P1-P3P4-P6P7-P9P10-P12P13-P15P16-P18P19-P21P22-P24P25-P26
2009 Microchip Technology Inc. DS21682E-page 1
24LCS22A
Features:
• Single Supply with Operation down to 2.5V
• Supports Enhanced EDID
™
(E-EDID
™
) 1.3
• Completely Implements DDC1
™
/DDC2
™
Inter-
face for Monitor Identification, including Recovery
to DDC1
• 2 Kbit Serial EEPROM Low-Power CMOS
Technology:
- 1 mA active current, typical
-10A standby current, typical at 5.5V
• 2-Wire Serial Interface Bus, I
2
C
™
Compatible
• 100 kHz (2.5V) and 400 kHz (5V) Compatibility
• Self-Timed Write Cycle (including Auto-Erase)
• Hardware Write-Protect Pin
• Page Write Buffer for up to Eight Bytes
• 1,000,000 Erase Write Cycles
• Data Retention >200 years
• ESD Protection >4000V
• 8-pin PDIP and SOIC Packages
• Available Temperature Ranges:
• Pb-Free and RoHS Compliant
Description:
The Microchip Technology Inc. 24LCS22A is a 256 x 8-bit
dual-mode Electrically Erasable PROM (EEPROM). This
device is designed for use in applications requiring
storage and serial transmission of configuration and
control information. Two modes of operation have been
implemented: Transmit-Only mode (1 Kbit) and
Bidirectional mode (2 Kbit). Upon power-up, the device
will be in the Transmit-Only mode, sending a serial bit
stream of the memory array from 00h to 7Fh, clocked by
the VCLK pin. A valid high-to-low transition on the SCL pin
will cause the device to enter the Transition mode, and
look for a valid control byte on the I
2
C bus. If it detects a
valid control byte from the master, it will switch into
Bidirectional mode, with byte selectable read/write
capability of the entire 2K memory array using SCL. If no
control byte is received, the device will revert to the Trans-
mit-Only mode after it receives 128 consecutive VCLK
pulses while the SCL pin is idle. The 24LCS22A is avail-
able in standard 8-pin PDIP and SOIC packages. The
24LCS22A features a flexible write-protect pin which is
enabled by writing to address 7Fh (usually the checksum
in VESA
®
applications.
Package Types
Block Diagram
- Industrial (I) -40°C to +85°C
PDIP/SOIC
24LCS22A
*NC
*NC
WP
VSS
1
2
3
4
8
7
6
5
V
CC
VCLK
SCL
SDA
* Pins labeled ‘NC’ have no internal connection
HV Generator
EEPROM
Array
Page Latches
YDEC
XDEC
Sense Amp.
R/W Control
Memory
Control
Logic
I/O
Control
Logic
WP
SDA SCL
Vcc
Vss
VCLK
2K VESA
®
E-EDID
™
Serial EEPROM
24LCS22A
DS21682E-page 2 2009 Microchip Technology Inc.
1.0 ELECTRICAL CHARACTERISTICS
Absolute Maximum Ratings
(†)
VCC.............................................................................................................................................................................7.0V
All inputs and outputs w.r.t. V
SS ......................................................................................................... -0.6V to VCC +1.0V
Storage temperature ...............................................................................................................................-65C to +150C
Ambient temperature with power applied................................................................................................-40C to +125C
ESD protection on all pins 4kV
TABLE 1-1: DC CHARACTERISTICS
† Notice: Stresses above those listed under “Absolute Maximum Ratings” may cause permanent damage to the
device. This is a stress rating only and functional operation of the device at those or any other conditions above those
indicated in the operational listings of this specification is not implied. Exposure to maximum rating conditions for
extended periods may affect device reliability.
DC CHARACTERISTICS
Vcc = +2.5V to 5.5V
Industrial (I): T
A = -40°C to +85°C
Param.
No.
Sym Characteristic Min. Max. Units Test Conditions
SCL and SDA pins:
D1 V
IH High-level input voltage 0.7 VCC —V
D2 VIL Low-level input voltage — 0.3 VCC V
Input levels on VCLK pin:
D3 V
IH High-level input voltage 2.0 — V VCC 2.7V (Note)
D4 VIL Low-level input voltage — 0.2 VCC VVCC 2.7V (Note)
D5 VHYS Hysteresis of Schmitt Trigger
Inputs
.05 VCC —V(Note)
D6 V
OL1 Low-level output voltage — 0.4 V IOL = 3 mA, VCC = 2.5V (Note)
D7 VOL2 Low-level output voltage — 0.6 V IOL = 6 mA, VCC = 2.5V
D8 I
LI Input leakage current — ±1 AVIN = 0.1V to VCC
D9 ILO Output leakage current — ±1 AVOUT = 0.1V to VCC
D10 CIN, COUT Pin capacitance
(all inputs/outputs)
—10pFVCC = 5.0V (Note)
T
A = 25°C, FCLK = 1 MHz
Operating current:
D10 I
CC WRITE Operating current — 3 mA VCC = 5.5V,
D11 I
CC READ Operating current — 1 mA VCC = 5.5V, SCL = 400 kHz
D12 ICCS Standby current —
—
30
100
A
A
VCC = 3.0V, SDA = SCL = VCC
VCC = 5.5V, SDA = SCL = VCC
VCLK = VSS
Note: This parameter is periodically sampled and not 100% tested.
2009 Microchip Technology Inc. DS21682E-page 3
24LCS22A
TABLE 1-2: AC CHARACTERISTICS
AC CHARACTERISTICS
Vcc = +2.5V to 5.5V
Industrial (I): T
A = -40°C to +85°C
Param.
No.
Sym Parameter Min Max Units Conditions
1F
CLK Clock frequency —
—
100
400
kHz 2.5V VCC 5.5V
4.5V V
CC 5.5V
2T
HIGH Clock high time 4000
600
—
—
ns 2.5V VCC 5.5V
4.5V V
CC 5.5V
3T
LOW Clock low time 4700
1300
—
—
ns 2.5V VCC 5.5V
4.5V V
CC 5.5V
4T
R SDA and SCL rise time —
—
1000
300
ns 2.5V VCC 5.5V (Note 1)
4.5V V
CC 5.5V (Note 1)
5T
F SDA and SCL fall time —
—
300
300
ns (Note 1)
6T
HD:STA Start condition hold time 4000
600
—
—
ns 2.5V VCC 5.5V
4.5V V
CC 5.5V
7T
SU:STA Start condition setup time 4700
600
—
—
ns 2.5V VCC 5.5V
4.5V V
CC 5.5V
8T
HD:DAT Data input hold time 0
0
—
—
ns (Note 2)
9T
SU:DAT Data input setup time 250
100
—
—
ns 2.5V VCC 5.5V
4.5V V
CC 5.5V
10 T
SU:STO Stop condition setup time 4000
600
—
—
ns 2.5V VCC 5.5V
4.5V V
CC 5.5V
11 T
AA Output valid from clock
(Note 2)
—
—
3500
900
ns 2.5V VCC 5.5V
4.5V V
CC 5.5V
12 T
BUF Bus free time: Time the bus must be
free before a new transmission can
start
4700
1300
—
—
ns 2.5V VCC 5.5V
4.5V V
CC 5.5V
13 T
OF Output fall time from VIH
minimum to VIL maximum
—
20+0.1CB
250
250
ns 2.5V VCC 5.5V (Note 1)
4.5V V
CC 5.5V (Note 1)
14 T
SP Input filter spike suppression
(SDA and SCL pins)
—
—
50
50
ns (Notes 1 and 3)
15 T
WR Write cycle time (byte or page) —
—
10
10
ms
16 T
VAA Output valid from VCLK —
—
2000
1000
ns
17 T
VHIGH VCLK high time 4000
600
—
—
ns
18 T
VLOW VCLK low time 4700
1300
—
—
ns
19 T
VHST VCLK setup time 0
0
—
—
ns
20 T
SPVL VCLK hold time 4000
600
—
—
ns
21 T
VHZ Mode transition time —
—
1000
500
ns
22 T
VPU Transmit-only power-up time 0
0
—
—
ns
23 T
SPV Input filter spike suppression (VCLK
pin)
—
—
100
100
ns
24 — Endurance 1M — cycles 25°C, V
CC = 5.0V, Block mode
(Note 4)
Note 1: Not 100% tested. CB = total capacitance of one bus line in pF.
2: As a transmitter, the device must provide an internal minimum delay time to bridge the undefined region (minimum 300 ns) of the
falling edge of SCL to avoid unintended generation of Start or Stop conditions.
3: The combined T
SP and VHYS specifications are due to Schmitt Trigger inputs which provide improved noise spike suppression.
This eliminates the need for a TI specification for standard operation.
4: This parameter is not tested but established by characterization. For endurance estimates in a specific application, please consult
the Total Endurance™ Model which can be obtained from Microchip’s web site at www.microchip.com.
P1-P3P4-P6P7-P9P10-P12P13-P15P16-P18P19-P21P22-P24P25-P26

24LCS22A-I/P

Mfr. #:
Buy 24LCS22A-I/P
Manufacturer:
Microchip Technology
Description:
EEPROM VESA E-EDID
Lifecycle:
New from this manufacturer.
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