24LCS22A
DS21682E-page 12 2009 Microchip Technology Inc.
6.0 WRITE PROTECTION
When using the 24LCS22A in the Bidirectional mode,
the VCLK pin can be used as a write-protect control
pin. Setting VCLK high allows normal write operations,
while setting VCLK low prevents writing to any location
in the array. Connecting the VCLK pin to VSS would
allow the 24LCS22A to operate as a serial ROM,
although this configuration would prevent using the
device in the Transmit-Only mode.
Additionally, pin 3 performs a flexible write-protect
function. The 24LCS22A contains a write protection
control fuse whose factory default state is cleared.
Writing any data to address 7Fh (normally the
checksum in DDC applications) sets the fuse which
enables the WP
pin. Until this fuse is set, the
24LCS22A is always write enabled (if VCLK = 1). After
the fuse is set, the write capability of the 24LCS22A is
determined by both VCLK and WP
pins (Table 6-1).
TABLE 6-1: WRITE-PROTECT TRUTH
TABLE
7.0 READ OPERATION
Read operations are initiated in the same way as write
operations with the exception that the R/W
bit of the
slave address is set to one. There are three basic types
of read operations: current address read, random read
and sequential read.
7.1 Current Address Read
The 24LCS22A contains an address counter that
maintains the address of the last word accessed,
internally incremented by one. Therefore, if the
previous access (either a read or write operation) was
to address n, the next current address read operation
would access data from address n + 1. Upon receipt of
the slave address with R/W
bit set to one, the
24LCS22A issues an acknowledge and transmits the
eight bit data word. The master will not acknowledge
the transfer, but does generate a Stop condition and the
24LCS22A discontinues transmission (Figure 7-1).
FIGURE 7-1: CURRENT ADDRESS
READ
7.2 Random Read
Random read operations allow the master to access
any memory location in a random manner. To perform
this type of read operation, first the word address must
be set. This is done by sending the word address to the
24LCS22A as part of a write operation. After the word
address is sent, the master generates a Start condition
following the acknowledge. This terminates the write
operation, but not before the internal Address Pointer is
set. Then the master issues the control byte again but
with the R/W
bit set to a one. The 24LCS22A will then
issue an acknowledge and transmits the 8-bit data
word. The master will not acknowledge the transfer, but
does generate a Stop condition and the 24LCS22A
discontinues transmission (Figure 7-2).
VCLK WP
Address
7Fh Written
Mode
for
00h-7Fh
0 XXRead-only
1 X No R/W
1 1/open X R/W
1 0 Yes Read-only
Control
A
C
K
SP
Byte
Data n
Bus Activity
SDA Line
Bus Activity
A
C
K
N
O
Master
101
0000
1
S
T
O
P
S
T
A
R
T
