24LCS22A
DS21682E-page 4 2009 Microchip Technology Inc.
2.0 FUNCTIONAL DESCRIPTION
The 24LCS22A is designed to comply to the DDC
Standard proposed by VESA (Figure 3-3) with the
exception that it is not Access.bus™ capable. It oper-
ates in two modes, the Transmit-Only mode (1 Kbit)
and the Bidirectional mode (2 Kbit). There is a separate
2-wire protocol to support each mode, each having a
separate clock input but sharing a common data line
(SDA). The device enters the Transmit-Only mode
upon power-up. In this mode, the device transmits data
bits on the SDA pin in response to a clock signal on the
VCLK pin. The device will remain in this mode until a
valid high-to-low transition is placed on the SCL input.
When a valid transition on SCL is recognized, the
device will switch into the Bidirectional mode and look
for its control byte to be sent by the master. If it detects
its control byte, it will stay in the Bidirectional mode.
Otherwise, it will revert to the Transmit-Only mode after
it sees 128 VCLK pulses.
2.1 Transmit-Only Mode
The device will power up in the Transmit-Only mode at
address 00h. This mode supports a unidirectional
2-wire protocol for continuous transmission of the first
1 Kbit of the memory array. This device requires that it
be initialized prior to valid data being sent in the Trans-
mit-Only mode (Section 2.2 “Initialization Proce-
dure”). In this mode, data is transmitted on the SDA
pin in 8-bit bytes, with each byte followed by a ninth,
Null bit (Figure 2-1). The clock source for the Transmit-
Only mode is provided on the VCLK pin, and a data bit
is output on the rising edge on this pin. The eight bits in
each byte are transmitted Most Significant bit first.
Each byte within the memory array will be output in
sequence. After address 7Fh in the memory array is
transmitted, the internal Address Pointers will wrap
around to the first memory location (00h) and continue.
The Bidirectional mode clock (SCL) pin must be held
high for the device to remain in the Transmit-Only
mode.
2.2 Initialization Procedure
After VCC has stabilized, the device will be in the Trans-
mit-Only mode. Nine clock cycles on the VCLK pin
must be given to the device for it to perform internal
sychronization. During this period, the SDA pin will be
in a high-impedance state. On the rising edge of the
tenth clock cycle, the device will output the first valid
data bit which will be the Most Significant bit in address
00h. (Figure 2-2).
FIGURE 2-1: TRANSMIT-ONLY MODE
FIGURE 2-2: DEVICE INITIALIZATION
SCL
SDA
VCLK
T
VAA TVAA
Bit 1 (LSB)
Null Bit
Bit 1 (MSB) Bit 7
T
VLOWTVHIGH
TVAA TVAA
Bit 8 Bit 7High-impedance for 9 clock cycles
TVPU
12 891011
SCL
SDA
VCLK
V
CC
