ADM1021A
Rev. 7 | Page 3 of 19 | www.onsemi.com
SPECIFICATIONS
T
A
= T
MIN
to T
MAX
1
, V
DD
= 3.0 V to 3.6 V, unless otherwise noted.
Table 1.
Parameter Min Typ Max Unit Test Conditions/Comments
POWER SUPPLY AND ADC
Temperature Resolution 1 °C Guaranteed no missed codes
Temperature Error, Local Sensor ±1 °C
−3 +3 °C
Temperature Error, Remote Sensor −3 +3 °C T
A
= 60°C to 100°C
−5 +5 °C
Supply Voltage Range
2
3 3.6 V
Undervoltage Lockout Threshold 2.5 2.7 2.95 V V
DD
input, disables ADC, rising edge
Undervoltage Lockout Hysteresis 25 mV
Power-On Reset Threshold 0.9 1.7 2.2 V V
DD
, falling edge
3
POR Threshold Hysteresis 50 mV
Standby Supply Current 1 5 μA V
DD
= 3.3 V, no SMBus activity
4 μA SCLK at 10 kHz
Average Operating Supply Current 130 200 μA 0.25 conversions/sec rate
Autoconvert Mode, Averaged Over 4 Seconds 225 370 μA 2 conversions/sec rate
Conversion Time 65 115 170 ms From stop bit to conversion complete (both channels)
D+ forced to D− + 0.65 V
Remote Sensor Source Current 120 205 300 μA
High level
3
7 12 16 μA
Low level
3
D− Source Voltage 0.7 V
Address Pin Bias Current (ADD0, ADD1) 50 μA Momentary at power-on reset
SMBUS INTERFACE
Logic Input High Voltage, V
IH
STBY
, SCLK, SDATA 2.2 V V
DD
= 3 V to 5.5 V
Logic Input Low Voltage, V
IL
STBY
, SCLK, SDATA 0.8 V V
DD
= 3 V to 5.5 V
SMBus Output Low Sink Current 6 mA SDATA forced to 0.6 V
ALERT
Output Low Sink Current 1 mA
ALERT
forced to 0.4 V
Logic Input Current, I
IH
, I
IL
−1 +1 μA
SMBus Input Capacitance, SCLK, SDATA 5 pF
SMBus Clock Frequency 100 kHz
SMBus Clock Low Time, t
LOW
4.7 μs t
LOW
between 10% points
SMBus Clock High Time, t
HIGH
4 μs t
HIGH
between 90% points
SMBus Start Condition Setup Time, t
SU:STA
4.7 μs
SMBus Repeat Start Condition 250 ns
Setup Time, t
SU:STA
250 ns Between 90% and 90% points
SMBus Start Condition Hold Time, t
HD:STA
4 μs Time from 10% of SDATA to 90% of SCLK
SMBus Stop Condition Setup Time, t
SU:STO
4 μs Time from 90% of SCLK to 10% of SDATA
SMBus Data Valid to SCLK 250 ns Time from 10% or 90% of SDATA to 10% of SCLK
Rising Edge Time, t
SU:DAT
250 ns Time from 10% or 90% of SDATA to 10% of SCLK
SMBus Data Hold Time, t
HD:DAT
0 μs
SMBus Bus Free Time, t
BUF
4.7 μs Between start/stop conditions
SCLK Falling Edge to SDATA 1
Valid Time, t
VD, DAT
1 μs Master clocking in data
1
T
MAX
= 100°C; T
MIN
= 0°C.
2
Operation at V
DD
= 5 V guaranteed by design, not production tested.
3
Guaranteed by design, not production tested.
