9
AT24C1024
1471I–SEEPR–7/03
Device
Addressing
The 1024K EEPROM requires an 8-bit device address word following a start condition to
enable the chip for a read or write operation (refer to Figure 1). The device address word con-
sists of a mandatory one, zero sequence for the first five most significant bits as shown. This is
common to all 2-wire EEPROM devices.
The 1024K uses the one device address bit, A1, to allow up to two devices on the same bus.
The A1 bit must compare to the corresponding hardwired input pin. The A1 pin uses an inter-
nal proprietary circuit that biases it to a logic low condition if the pin is allowed to float.
The seventh bit (P
0
) of the device address is a memory page address bit. This memory page
address bit is the most significant bit of the data word address that follows. The eighth bit of
the device address is the read/write operation select bit. A read operation is initiated if this bit
is high and a write operation is initiated if this bit is low.
Upon a compare of the device address, the EEPROM will output a zero. If a compare is not
made, the device will return to a standby state.
DATA SECURITY: The AT24C1024 has a hardware data protection scheme that allows the
user to write-protect the entire memory when the WP pin is at V
CC
.
Write
Operations
BYTE WRITE: To select a data word in the 1024K memory requires a 17-bit word address.
The word address field consists of the P
0
bit of the device address, then the most significant
word address followed by the least significant word address (refer to Figure 2)
A write operation requires the P
0
bit and two 8-bit data word addresses following the device
address word and acknowledgment. Upon receipt of this address, the EEPROM will again
respond with a zero and then clock in the first 8-bit data word. Following receipt of the 8-bit
data word, the EEPROM will output a zero. The addressing device, such as a microcontroller,
then must terminate the write sequence with a stop condition. At this time the EEPROM enters
an internally timed write cycle, T
WR
, to the nonvolatile memory. All inputs are disabled during
this write cycle and the EEPROM will not respond until the write is complete (refer to Figure 2).
PAGE WRITE: The 1024K EEPROM is capable of 256-byte page writes.
A page write is initiated the same way as a byte write, but the microcontroller does not send a
stop condition after the first data word is clocked in. Instead, after the EEPROM acknowledges
receipt of the first data word, the microcontroller can transmit up to 255 more data words. The
EEPROM will respond with a zero after each data word received. The microcontroller must ter-
minate the page write sequence with a stop condition (refer to Figure 3).
The data word address lower 8 bits are internally incremented following the receipt of each
data word. The higher data word address bits are not incremented, retaining the memory page
row location. When the word address, internally generated, reaches the page boundary, the
following byte is placed at the beginning of the same page. If more than 256 data words are
transmitted to the EEPROM, the data word address will “roll over” and previous data will be
overwritten. The address “rollover” during write is from the last byte of the current page to the
first byte of the same page.
ACKNOWLEDGE POLLING: Once the internally timed write cycle has started and the
EEPROM inputs are disabled, acknowledge polling can be initiated. This involves sending a
start condition followed by the device address word. The read/write bit is representative of the
operation desired. Only if the internal write cycle has completed will the EEPROM respond
with a zero, allowing the read or write sequence to continue.
