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VNLD5090TR-E

P1-P3P4-P6P7-P9P10-P12P13-P15P16-P18P19-P20
Electical specifications VNLD5090-E
10/20 DocID023206 Rev 4
Figure 4. Switching characteristics
Table 12. Truth table
Conditions INPUT DRAIN STATUS
Normal operation
L
H
H
L
H
H
Current limitation
L
H
H
X
H
H
Overtemperature
L
H
H
H
H
L
Undervoltage
L
H
H
H
X
X
DocID023206 Rev 4 11/20
VNLD5090-E Application information
19
3 Application information
Figure 5. Application schematic
3.1 MCU I/O protection
ST suggests to insert a resistor (R
prot
) in line to prevent the microcontroller I/O pins from
latching up
(a)
. The value of these resistors is a compromise between the leakage current of
microcontroller and the current required by the LSD I/Os (input levels compatibility) with the
latch-up limit of microcontroller I/Os:
Equation 1
Let:
• I
latchup
> 20 mA
• V
OHµC
> 4.5 V
• 35 Ω ≤ R
prot
≤ 100 KΩ
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a. In case of negative transient on the drain pin.
0.7
I
latchup
-------------------- R
prot
V
OHμC
V
IH
–()
I
IH max
----------------------------------------≤≤
Application information VNLD5090-E
12/20 DocID023206 Rev 4
Then, the recommended value is R
prot
= 1 KΩ
Figure 6 shows the turn-off current drawn during the demagnetization.
Figure 6. Maximum demagnetization energy (V
CC
= 16 V)
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P1-P3P4-P6P7-P9P10-P12P13-P15P16-P18P19-P20

VNLD5090TR-E

Mfr. #:
Buy VNLD5090TR-E
Manufacturer:
STMicroelectronics
Description:
Gate Drivers OMNIFET III fully protect lo-side drvr
Lifecycle:
New from this manufacturer.
Delivery:
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