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VNLD5090TR-E

P1-P3P4-P6P7-P9P10-P12P13-P15P16-P18P19-P20
DocID023206 Rev 4 13/20
VNLD5090-E Package and PC board thermal data
19
4 Package and PC board thermal data
4.1 SO-8 thermal data
Figure 7. SO-8 PC board
Note: Layout condition of R
th
and Z
th
measurements (Board finish thickness 1.6 mm +/- 10%;
Board double layer; Board dimension 78
mm x 86 mm; Board Material FR4; Cu thickness
0.070
mm (front and back side); Thermal vias separation 1.2 mm; Thermal via diameter
0.3
mm +/- 0.08 mm; Cu thickness on vias 0.025 mm).
Figure 8.
SO-8 R
thj-amb
vs PCB copper area in open box free air condition
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





  
57+MDPE
("1($'5
Package and PC board thermal data VNLD5090-E
14/20 DocID023206 Rev 4
Figure 9. SO-8 thermal impedance junction ambient single pulse
Equation 2: pulse calculation formula
where δ
=
t
P
/T
Figure 10. Thermal fitting model of a LSD in SO-8
Note: The fitting model is a semplified thermal tool and is valid for transient evolutions where the
embedded protections (power limitation or thermal cycling during thermal shutdown) are not
triggered.
Z
THδ
R
TH
δ Z
THtp
1 δ–()+⋅=
("1($'5
DocID023206 Rev 4 15/20
VNLD5090-E Package and PC board thermal data
19
Table 13. SO-8 thermal parameters
Area/island (cm
2
) Footprint 2
R1 = R7 (°C/W) 0.8 0.8
R2 = R8 (°C/W) 2.7 2.7
R3 = R9 (°C/W) 1.5 1.5
R4 = R10 (°C/W) 32 25
R5 (°C/W) 36 20
R6 (°C/W) 35 27
C1 = C7 (W.s/°C) 0.00005 0.00005
C2 = C8 (W.s/°C) 0.001 0.001
C3 = C9 (W.s/°C) 0.01 0.01
C4 = C10 (W.s/°C) 0.02 0.02
C5 (W.s/°C) 0.1 0.15
C6 (W.s/°C) 2.5 3.5
P1-P3P4-P6P7-P9P10-P12P13-P15P16-P18P19-P20

VNLD5090TR-E

Mfr. #:
Buy VNLD5090TR-E
Manufacturer:
STMicroelectronics
Description:
Gate Drivers OMNIFET III fully protect lo-side drvr
Lifecycle:
New from this manufacturer.
Delivery:
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