List of figures VNLD5090-E
4/20 DocID023206 Rev 4
List of figures
Figure 1. Block diagram. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5
Figure 2. Current and voltage conventions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6
Figure 3. Configuration diagrams (top view) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6
Figure 4. Switching characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10
Figure 5. Application schematic . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 11
Figure 6. Maximum demagnetization energy (V
CC
= 16 V) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 12
Figure 7. SO-8 PC board . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 13
Figure 8. SO-8 Rthj-amb vs PCB copper area in open box free air condition . . . . . . . . . . . . . . . . . . 13
Figure 9. SO-8 thermal impedance junction ambient single pulse. . . . . . . . . . . . . . . . . . . . . . . . . . . 14
Figure 10. Thermal fitting model of a LSD in SO-8 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 14
Figure 11. SO-8 package dimensions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 16
Figure 12. SO-8 tube shipment (no suffix) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 18
Figure 13. SO-8 tape and reel shipment (suffix “TR”) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 18
DocID023206 Rev 4 5/20
VNLD5090-E Block diagrams and pins configurations
19
1 Block diagrams and pins configurations
Figure 1. Block diagram
Table 2. Pin function
Name Function
IN
1,2
/VSUPPLY
1,2
Voltage controlled input pin with hysteresis, CMOS compatible. They controls
output switch state
DRAIN
1,2
PowerMOS drain
SOURCE
1,2
PowerMOS source and ground reference for the control section
STATUS
1,2
Open drain digital diagnostic pin
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Block diagrams and pins configurations VNLD5090-E
6/20 DocID023206 Rev 4
Figure 2. Current and voltage conventions
Figure 3. Configuration diagrams (top view)
Table 3. Suggested connections for unused and n.c. pins
Connection / pin STATUS
1,2
N.C. INPUT
1,2
Floating X
(1)
1. X: do not care.
XX
To ground Not allowed X Through 10 kΩ resistor
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VNLD5090TR-E

Mfr. #:
Manufacturer:
STMicroelectronics
Description:
Gate Drivers OMNIFET III fully protect lo-side drvr
Lifecycle:
New from this manufacturer.
Delivery:
DHL FedEx Ups TNT EMS
Payment:
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