PIN # PIN NAM E TYPE DESC RIPTION
25 SRCC3/CR#_D I/O
Complementary cloc k of differential SRC clock pair/ Clock Reques t control D for either SRC1 or SRC4 pair
The power-up default is SRCC LK3 output, but this pin may also be us ed as a Clock Request control of SRC pair 1 or SRC pair 4
via SMBus . Before c onfiguring this pin as a Cloc k Request Pin, the SR C output mus t first be disabled in byte 4, bit 7 of SMBus
address s pace . After the SR C output is disabled, the pin c an then be set to serve as a Cloc k Request pin for either SRC pair 1 or
pair 4 us ing the CRD#_EN bit located in byte 5 of SMBUs addres s space.
By te 5, bit 1
0 = SRC 3 enabled (default)
1= CR D# enabled. Byte 5, bit 0 controls whether CRD # controls SR C1 or SRC4 pair
Byte 5, bit 0
0 = CRD# controls SRC1 pair (default),
1= CR D# c ontrols SRC4 pair
26 VDDSRC_IO PWR Power supply for SR C c locks. 0.8V nominal from source/emitter of ex ternal pas s transis tor
27 SRCT4 O UT True c loc k of low power differential SRC c loc k pair.
28 SRCC4 O UT Complement clock of low power differential SRC clock pair.
29 CPU_ST O P#/SRCC5 I/O Ref, XT AL power supply, nominal 3.3V
30 PCI_ST O P#/SRCT5 I/O
Stops all PCICLKs at logic 0 lev el, when low. Free running PC ICLKs are not effec ted by this input. / True c loc k of differential pus h-
pull SRC pair.
31 VDDSRC PWR Supply for SRC PLL, 3.3V nominal
32 SRCC6 O UT Complement clock of low power differential SRC clock pair.
33 SRCT6 O UT True c loc k of low power differential SRC c loc k pair.
34 G NDSRC PWR G round pin for the SR C outputs
35 SRCC7/CR#_E I/O
Complement clock of differential push-pull SR C c loc k pair. / Cloc k Reques t c ontrol E for SRC6 pair. The power-up default is
SRC7#, but this pin may also be us ed as a Clock Reques t control of SRC6 via SMBus . Before c onfiguring this pin as a Clock
Request Pin, the SRC 7 output pair mus t first be disabled in byte 3, bit 3 of SMBus c onfiguration space . After the SRC output is
disabled (high-Z), the pin can then be set to s erve as a Clock Request for SRC6 pair us ing by te 6, bit 7 of SMBus configuration
space
By te 6, bit 7
0 = SRC 7# enabled (default)
1= CR E# enabled.
36 SRCT7/CR#_F I/O
True c loc k of differential pus h-pull SRC cloc k pair/ Clock Reques t control 8 for SR C8 pair
The power-up default is SRC7, but this pin may also be us ed as a Cloc k Request control of SRC8 via SMBus. Before c onfiguring
this pin as a Clock Reques t Pin, the SRC7 output pair must first be disabled in by te 3, bit 3 of SMBus configuration space After the
SRC output is disabled (high-Z), the pin c an then be set to s erve as a Clock Request for SRC 8 pair us ing by te 6, bit 6 of SMBus
configuration s pac e.
By te 6, bit 6
0 = SRC 7# enabled (default)
1 = CRF# enabled.
37 VDDSRC_IO PWR Power supply for SR C c locks. 0.8V nominal from source/emitter of ex ternal pas s transis tor
38 CPUC2_IT P/SRCC8 O UT
Complement clock of low power differential CPU2/Complement clock of differential SRC pair. The function of this pin is determined
by the latched input value on pin 7, PCIF5/ITP_EN on powerup. The function is as follows:
Pin 7 latc hed input Value
0 = SRC 8#
1 = ITP#
39 CPUT2_IT P/SR CT8 O UT
True c loc k of low power differential CPU2/True clock of differential SRC pair. The function of this pin is determined by the latched
input v alue on pin 7, PCIF5/ITP_EN on powerup. T he function is as follows :
Pin 7 latc hed input Value
0 = SRC 8
1 = ITP
40 VOUT PWR O P Amp comparator output. This pin drives the base/gate of the ex ternal pass trans istor
41 VDDCPU_IO PWR Supply for CPU clock s . 0.8V nominal from source/emitter of external pass trans istor
42 CPUC1_F O UT Complementary cloc k of low power differential pus h-pull CPU output. This CPU clock is free running during iAMT.
43 CPUT1_F O UT True clock of differential push-pull CPU clock pair. This clock is free running during iAMT.
44 G NDC PU PWR G round pin for the CPU outputs
45 CPUC0 O UT Complement clock of low power differential CPU clock pair.
46 CPUT0 O UT True c loc k of low power differential CPU cloc k pair.
47 VDDCPU PWR Supply for CPU PLL, 3.3V nominal
48 CK_PWRG D /PD# IN Notifies CK505 to sample latched inputs , or iAMT entry/exit, or PWRDWN# mode
49 FSLB/TEST _MODE IN
3.3V tolerant input for CPU frequency selection. R efer to input elec tric al charac teristics for Vil_FS and Vih_F S values .
TEST _MODE is a real time input to select between Hi-Z and REF/N divider mode while in test mode. Refer to Tes t Clarific ation
Table.
50 G NDR EF PWR G round pin for the REF outputs.
51 X2 O UT Cry stal output, Nominally 14.318MHz
52 X1 IN Cry stal input, Nominally 14.318MHz.
53 VDDREF PWR Ref, XTAL power supply, nominal 3.3V
54 REF0/F SLC/TEST_SEL I/O
14.318 MHz referenc e clock./ 3.3V tolerant input for CPU frequency selection. Refer to input electrical characteristics for Vil_FS
and Vih_F S values . /TEST_Sel: 3-level latc hed input to enable tes t mode. Refer to Tes t Clarification Table
55 SDATA I/O Data pin for SMBus c ircuitry , 5V tolerant.
56 SCLK IN Clock pin of SMBus circuitry , 5V tolerant.
