IDT
TM
/ICS
TM
PC MAIN CLOCK 1397—11/08/10
ICS9LP525-2
PC MAIN CLOCK
7
C lock Jitter Specs - Low Power D ifferential Outputs
PARA M E TER SYMBOL CONDITIONS M IN M A X UNITS NOTE S
CP U J itter - Cyc le to Cycle CP UJ C2C Differential M eas urem ent 85 ps 1
SRC J itter - Cyc le to Cycle SRCJ C2C Differential M eas urem ent 125 ps 1,2
DOT J itter - Cyc le to Cycle DOTJ C2C Differential M eas urem ent 250 ps 1
1
JItter spec s are spec ified as m easured on a cloc k c har acterization board. Sy stem designers need to tak e s pecial c are not to us e these numbers , as the in-sy s tem performance will be
som ewhat degraded. T he rec eiver EMT S (c hispet or CPU ) w ill hav e the rec eiver jitter s pec s as m easured ina real s ystem.
2
Phas e jitter requirement: The deisgnated G e2 outputs w ill m eet the reference c loc k jitter requiremernts from the PC I Ex pres s G en2 Bas e Spec . The tes t is perform ed on a com ponnet
tes t board under quiet c ondittions w ith all outputs on. J itter analys is is performed us ing the standardized tool prov ided by the PCI SIG .
NO TES o n DIF O u tput Jitter: ( un less oth erw ise n ot ed, g uaranteed b y d esig n and characteriz ation , no t 100% tested in prod uct io n).
AC Electrical Characteristics - Low Power Differential Outputs
PARAMETER SYMBOL CONDITIONS MIN MAX UNITS NOTES
Rising Edge Slew Rate tSLR Averaging on 2.5 4 V/ns 2, 3
Falling Edge Slew Rate tFLR Averaging on 2.5 4 V/ns 2, 3
Slew Rate Variation tSLVAR Averaging on 20 % 1, 10
Differential Voltage Swing VSWING Averaging off 300 mV 2
Crossing Point Voltage VXABS Averaging off 300 550 mV 1,4,5
Crossing Point Variation VXABSVAR Averaging off 140 mV 1,4,9
Maximum Output Voltage VHIGH Averaging off 1150 mV 1,7
Minimum Output Voltage VLOW Averaging off -300 mV 1,8
Duty Cycle DCYC Averaging on 45 55 % 2
CPU Skew CPUSKEW Averaging on 100 ps
CPU[1:0] Skew CPUSKEW10 Differential Measurement 100 ps 1
CPU[2_ITP:0] Skew CPUSKEW20 Differential Measurement 150 ps 1
SRC[10:0] Skew SRCSKEW Differential Measurement 3000 ps 1,6,11
1
Measurement taken for single ended waveform on a component test board (not in system)
2
Measurement taken from differential waveform on a component test board. (not in system)
3
Slew rate emastured through V_swing voltage range centered about differential zero
4
Vcross is defined at the voltage where Clock = Clock#, measured on a component test board (not in system)
5
Only applies to the differential rising edge (Clock rising, Clock# falling)
NOTES on DIF Output AC Specs: (unless otherwise noted, guaranteed by design and characterization, not 100% tested in production).
9
The total variation of all Vcross measurements in any particular system. Note this is a subset of V_cross min/mas (V_Cross absolute) allowed. The intent is to limit Vcross induced
modulation by setting C_cross_delta to be smaller than V_Cross absolute.
10
Matching applies to rising edge rate for Clock and falling edge rate for Clock#. It is measured using a +/-75mV window centered on the average cross point where Clock rising meets
Clock# falling. The median cross point is used to calculate the voltage thresholds the oscilloscope is to use for the edge rate calculations.
6
Total distributed intentional SRC to SRC skew. PCIE Gen2 outputs (SRC3, 4, 6 and 7) will have 0 nominal skew. Maximum allowable interpair skew is 150 ps.
7
The max voltage including overshoot.
8
The min voltage including undershoot.
11
For PCIe Gen2 compliant devices, SRC 3, 4, 6, and 7 will have 0 ps nominal skew.
NOTES on DC Parameters: (unless otherwise noted, guaranteed by design and characterization, not 100% tested in production).
1
Signal is required to be monotonic in this region.
2
input leakage current does not include inputs with pull-up or pull-down resistors
3
3.3V referenced inputs are: PCI_STOP#, CPU_STOP#, TME, SRC5_EN, ITP_EN, SCLKL, SDATA, TESTMODE, TESTSEL, CKPWRGD and CR# inputs if selected.
4
Intentionally blank
5
Maximum VIH is not to exceed VDD
6
Human Body Model
7
Operation under these conditions is neither implied, nor guaranteed.
8
Frequency Select pins which have tri-level input
9
PCI3/CFG0 is optional
10
If present. Not all parts have this feature.
IDT
TM
/ICS
TM
PC MAIN CLOCK 1397—11/08/10
ICS9LP525-2
PC MAIN CLOCK
8
CPU SRC DOT96 BMC133
100 100 100 100
ppm
85 125 250
125
ps
-0.50% -0.50% 0 -0.50% %
Clock Periods - Differential Outputs with Spread Spectrum Disabled
1 Clock 1us 0.1s 0.1s 0.1s 1us 1 Clock
-c2c jitter
AbsPer
Min
-SSC
Short-Term
Average
Min
- ppm
Long-Term
Average
Min
0 ppm
Period
Nominal
+ ppm
Long-Term
Average
Max
+SSC
Short-Term
Average
Max
+c2c jitter
AbsPer
Max
100.00 9.91400 9.99900 10.00000 10.00100 10.08600 ns 1,2
133.33 7.41425 7.49925 7.50000 7.50075 7.58575 ns 1,2
166.67 5.91440 5.99940 6.00000 6.00060 6.08560 ns 1,2
200.00 4.91450 4.99950 5.00000 5.00050 5.08550 ns 1,2
266.67 3.66462 3.74962 3.75000 3.75037 3.83537 ns 1,2
333.33 2.91470 2.99970 3.00000 3.00030 3.08530 ns 1,2
400.00 2.41475 2.49975 2.50000 2.50025 2.58525 ns 1,2
SRC/SATA 100.00 9.87400 9.99900 10.00000 10.00100 10.12600 ns 1,2
DOT96 96.00 10.16563 10.41563 10.41667 10.41771 10.66771 ns 1,2
Clock Periods - Differential Outputs with Spread Spectrum Enabled
1 Clock 1us 0.1s 0.1s 0.1s 1us 1 Clock
-c2c jitter
AbsPer
Min
-SSC
Short-Term
Average
Min
- ppm
Long-Term
Average
Min
0 ppm
Period
Nominal
+ ppm
Long-Term
Average
Max
+SSC
Short-Term
Average
Max
+c2c jitter
AbsPer
Max
99.75 9.91406 9.99906 10.02406 10.02506 10.02607 10.05107 10.13607 ns 1,2
133.00 7.41430 7.49930 7.51805 7.51880 7.51955 7.53830 7.62330 ns 1,2
166.25 5.91444 5.99944 6.01444 6.01504 6.01564 6.03064 6.11564 ns 1,2
199.50 4.91453 4.99953 5.01203 5.01253 5.01303 5.02553 5.11053 ns 1,2
266.00 3.66465 3.74965 3.75902 3.75940 3.75977 3.76915 3.85415 ns 1,2
332.50 2.91472 2.99972 3.00722 3.00752 3.00782 3.01532 3.10032 ns 1,2
399.00 2.41477 2.49977 2.50602 2.50627 2.50652 2.51277 2.59777 ns 1,2
SRC 99.75 9.87406 9.99906 10.02406 10.02506 10.02607 10.05107 10.17607 ns 1,2
1
Guaranteed by design and characterization, not 100% tested in production.
Measurement Window
Units
PPM tolerance
Cycle to Cycle Jitter
Spread
SSC OFF
Center
Freq.
MHz
Notes
Differential Clock Tolerances
CPU
2
All Long Term Accuracy specifications are guaranteed with the assumption that the crystal input is tuned to exactly 14.31818MHz.
Measurement Window
UnitsSSC ON
Center
Freq.
MHz
Notes
CPU
IDT
TM
/ICS
TM
PC MAIN CLOCK 1397—11/08/10
ICS9LP525-2
PC MAIN CLOCK
9
Intentional PCI Clock to Clock Delay
200 ps nominal steps
PCI0
PCI1
PCI2
PCI3
PCI4
PCI_F5
1.0ns
Electrical Characteristics - PC IC LK /PC IC LK _F
PARAM E TER SYMBOL CONDITIONS M IN M A X UNITS
NOTE S
Long A ccuracy ppm see Tperiod m in-max values -100 100 ppm 1,2
33.33M Hz output no spread 29.99700 30.00300 ns 2
33.33M Hz output spread 30.08421 30.23459 ns 2
33.33M Hz output no spread 29.49700 30.50300 ns 2
33.33M Hz output nominal/s pread 29.56617 30.58421 ns 2
Rising E dge S lew Rate t
SLR
M easured from 0.8 to 2.0 V 1 4 V /ns 1
Falling Edge Slew Rate t
FLR
M easured from 2.0 to 0.8 V 1 4 V /ns 1
Pin to P in S kew t
s k ew
V
T
= 1.5 V 250 ps 2
Intential P CI to P CI delay t
s k ew
V
T
= 1.5 V 100 200 ps 2
Duty Cy c le d
t1
V
T
= 1.5 V 45 55 % 2
Jitter, Cycle to cyc le t
jc yc -c y c
V
T
= 1.5 V 500 ps 2
T
abs
Absolute min/max period
Clock period T
period
Electrical Ch aracteristics - U S B 48MH z
PARA M E TER SYMBOL CONDITIONS MIN M A X UNITS
NOTE S
Long A ccuracy ppm s ee T period m in-m ax v alues -100 100 ppm 2,4
Clock period T
period
48.00M Hz output nominal 20.83125 20.83542 ns 2,3
Absolute min/max period T
abs
48.00M Hz output nominal 20.48125 21.18542 ns 2
CLK High Tim e T
HI G H
8.216563 11.15198 V
CLK Low tim e T
LOW
7.816563 10.95198 V
Rising E dge Slew Rate t
SLR
M easured from 0.8 to 2.0 V 1 2 V /ns 1
Falling Edge Slew Rate t
FLR
M easured from 2.0 to 0.8 V 1 2 V /ns 1
Duty Cy c le d
t1
V
T
= 1.5 V 45 55 % 2
Jitter, Cycle to cyc le t
jc yc -c y c
V
T
= 1.5 V 350 ps 2
Electrical Ch aracteris tics - R EF-14.318MH z
PARA M E TER S Y M B O L CONDITIONS MIN M A X UNITS Notes
Long A c curacy
ppm
s ee Tperiod min-max values
-100
100
ppm
2, 4
Clock period
Tperiod
14.318MHz output nom inal
69.82033
69.86224
ns
2, 3
Absolute min/max period Tabs 14.318MHz output nom inal 69.83400 70.84800 ns 2
CLK High Tim e THIGH 29.97543 38.46654 V
CLK Low tim e
TLO W
29.57543
38.26654
V
Rising E dge Slew Rate
tS LR
M eas ured from 0.8 to 2.0 V
1
4
V/ns
1
Falling E dge Slew Rate tFLR M eas ured from 2.0 to 0.8 V 1 4 V /ns 1
Duty Cyc le
dt1
VT = 1.5 V
45
55
%
2
Jitter, Cycle to cy cle
tjcyc-cyc
VT = 1.5 V
1000
ps
2
1
Edge rate in s ystem is measured from 0.8V to 2.0V.
2
Duty c ycle, Peroid and J itter are measured with res pect to 1.5V
3
The av erage period ov er any 1us period of time
4
Us ing frequency c ounter with th e meas urment interval equal or greater that 0.15s, target frequenc ies are 14.318180 MHz , 33.333333MH z and 48.000000M Hz
NO T ES o n SE outpu ts: (un less oth erw ise n oted , guaran teed by design and ch aracterizatio n, n ot 100% tested in produ ctio n).

9LP525BF-2LFT

Mfr. #:
Manufacturer:
IDT
Description:
Clock Synthesizer / Jitter Cleaner CK505 PCIe Gen2
Lifecycle:
New from this manufacturer.
Delivery:
DHL FedEx Ups TNT EMS
Payment:
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