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XC3042-125PQ100C

P1-P3P4-P6P7-P8
2-153
XC3000
Logic Cell Array Family
Features
• Industry-leading FPGA family with five device types
– Logic densities from 1,000 to 6,000 gates
– Up to 144 user-definable I/Os
• Guaranteed 70- to 125-MHz toggle rates, 9 to 5.5 ns
logic delays
• Advanced CMOS static memory technology
– Low quiescent and active power consumption
• XC3000-specific features
– Ultra-low current option in Power-Down mode
– 4-mA output sink and source current
– Broad range of package options includes plastic and
ceramic quad flat packs, plastic leaded chip carriers
and pin grid arrays
– 100% bitstream compatible with the XC3100 family
– Commercial, industrial, military, “high rel”, and MIL-
STD-883 Class B grade devices
– Easy migration to XC3300 series of HardWire mask-
programmed devices for high-volume production
User I/Os Horizontal Configuration
Device CLBs Array Max Flip-Flops Longlines Data Bits
XC3020 64 8 x 8 64 256 16 14,779
XC3030 100 10 x 10 80 360 20 22,176
XC3042 144 12 x 12 96 480 24 30,784
XC3064 224 16 x 14 120 688 32 46,064
XC3090 320 16 x 20 144 928 40 64,160
Product Specification
Description
XC3000 is the original family of devices in the XC3000
class of Field Programmable Gate Array (FPGA) architec-
tures. The XC3000 family has a proven track record in
addressing a wide range of design applications, including
general logic replacement and sub-systems integration.
For a thorough description of the XC3000 architecture see
the preceding pages of this data book.
The XC3000 Family covers a range of nominal device
densities from 2,000 to 9,000 gates, practically achievable
densities from 1,000 to 6,000 gates. Device speeds,
described in terms of maximum guaranteed toggle fre-
quencies, range from 70 to 125 MHz. The performance of
a completed design depends upon placement and routing
implementation, so, like with any gate array, the final
verification of device utilization and performance can only
be known after the design has been placed and routed.
IMPORTANT NOTICE
All new designs should use XC3000A.
Information on XC3000 is presented here
as a reference for existing designs.
XC3000 bitstreams are upward compatible
to XC3000A without modification.
XC3000 Logic Cell Array Family
2-154
Symbol
Description Units
V
CC
Supply voltage relative to GND –0.5 to +7.0 V
V
IN
Input voltage with respect to GND –0.5 to V
CC
+0.5 V
V
TS
Voltage applied to 3-state output –0.5 to V
CC
+0.5 V
T
STG
Storage temperature (ambient) –65 to +150 °C
T
SOL
Maximum soldering temperature (10 s @ 1/16 in.) +260 °C
Junction temperature plastic +125 °C
T
J
Junction temperature ceramic +150 °C
Note: Stresses beyond those listed under Absolute Maximum Ratings may cause permanent damage to the device.
These are stress ratings only, and functional operation of the device at these or any other conditions beyond
those listed under Recommended Operating Conditions is not implied. Exposure to Absolute Maximum
Ratings conditions for extended periods of time may affect device reliability.
Symbol Description Min Max Units
V
CC
Supply voltage relative to GND Commercial 0°C to +85°C junction 4.75 5.25 V
Supply voltage relative to GND Industrial -40°C to +100°C junction 4.5 5.5 V
V
IHT
High-level input voltage — TTL configuration 2.0 V
CC
V
V
ILT
Low-level input voltage — TTL configuration 0 0.8 V
V
IHC
High-level input voltage — CMOS configuration 70% 100% V
CC
V
ILC
Low-level input voltage — CMOS configuration 0 20% V
CC
T
IN
Input signal transition time 250 ns
Absolute Maximum Ratings
Operating Conditions
Xilinx maintains test specifications for each product as controlled documents. To insure the use of the most recently
released device performance parameters, please request a copy of the current test-specification revision.
At junction temperatures above those listed as Operating Conditions, all delay parameters increase by 0.3% per °C.
2-155
Symbol Description Min Max Units
V
OH
High-level output voltage (@ I
OH
= –4.0 mA, V
CC
min) 3.86 V
V
OL
Low-level output voltage (@ I
OL
= 4.0 mA, V
CC
min) 0.40 V
V
OH
High-level output voltage (@ I
OH
= –4.0 mA, V
CC
min) 3.76 V
V
OL
Low-level output voltage (@ I
OL
= 4.0 mA, V
CC
min) 0.40 V
V
CCPD
Power-down supply voltage (PWRDWN must be Low) 2.30 V
I
CCPD
Power-down supply current (V
CC(MAX)
@ T
MAX
)
1
XC3020 50 µA
XC3030 80 µA
XC3042 120 µA
XC3064 170 µA
XC3090 250 µA
I
CCO
Quiescent LCA supply current in addition to I
CCPD
2
Chip thresholds programmed as CMOS levels 500 µA
Chip thresholds programmed as TTL levels 10 mA
I
IL
Input Leakage Current –10 +10 µA
C
IN
Input capacitance, all packages except PGA175
(sample tested)
All Pins except XTL1 and XTL2 10 pF
XTL1 and XTL2 15 pF
Input capacitance, PGA 175
(sample tested)
All Pins except XTL1 and XTL2 15 pF
XTL1 and XTL2 20 pF
I
RIN
Pad pull-up (when selected) @ V
IN
= 0 V (sample tested) 0.02 0.17 mA
I
RLL
Horizontal Longline pull-up (when selected) @ logic Low 3.4 mA
Note: 1. Devices with much lower I
CCPD
tested and guaranteed at V
CC
= 3.2 V, T = 25°C can be ordered with a
Special Product Code.
XC3020 SPC0107: I
CCPD
= 1 µA
XC3030 SPC0107: I
CCPD
= 2 µA
XC3042 SPC0107: I
CCPD
= 3 µA
XC3064 SPC0107: I
CCPD
= 4 µA
XC3090 SPC0107: I
CCPD
= 5 µA
2. With no output current loads, no active input or Longline pull-up resistors, all package pins at V
CC
or GND,
and the LCA configured with a MakeBits tie option.
Industrial
Commercial
DC Characteristics Over Operating Conditions
P1-P3P4-P6P7-P8

XC3042-125PQ100C

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