2-157
Speed Grade -70 -100 -125
Description Symbol Min Max Min Max Min Max Units
Combinatorial Delay
Logic Variables A, B, C, D, E, to outputs X or Y 1 T
ILO
9.0 7.0 5.5 ns
Sequential delay
Clock k to outputs X or Y 8 T
CKO
6.0 5.0 4.5 ns
Clock k to outputs X or Y when Q is returned
through function generators F or G to drive X or Y T
QLO
13.0 10.0 8.0 ns
Set-up time before clock K
Logic Variables A, B, C, D, E 2 T
ICK
8.0 7.0 5.5 ns
Data In DI 4 T
DICK
5.0 4.0 3.0 ns
Enable Clock EC 6 T
ECCK
7.0 5.0 4.5 ns
Reset Direct inactive RD 1.0 1.0 1.0 ns
Hold Time after clock K
Logic Variables A, B, C, D, E 3 T
CKI
00 0ns
Data In DI 5 T
CKDI
4.0 2.0 1.5 ns
Enable Clock EC 7 T
CKEC
000ns
Clock
Clock High time 11 T
CH
5.0 4.0 3.0 ns
Clock Low time 12 T
CL
5.0 4.0 3.0 ns
Max flip-flop toggle rate F
CLK
70 100 125 MHz
Reset Direct (RD)
RD width 13 T
RPW
8.0 7.0 6.0 ns
delay from rd to outputs X or Y 9 T
RIO
8.0 7.0 6.0 ns
Global Reset (
RESET Pad)*
RESET width (Low) T
MRW
25.0 21.0 20.0 ns
delay from
RESET pad to outputs X or Y T
MRQ
23.0 19.0 17.0 ns
CLB Switching Characteristic Guidelines (continued)
Testing of the switching parameters is modeled after testing methods specified by MIL-M-38510/605. All devices are 100%
functionally tested. Since many internal timing parameters cannot be measured directly, they are derived from benchmark timing
patterns. The following guidelines reflect worst-case values over the recommended operating conditions. For more detailed, more
precise, and more up-to-date timing information, use the values provided by the XACT timing calculator and used in the simulator.
*Timing is based on the XC3042, for other devices see XACT timing calculator.
Note: The CLB K to Q output delay (T
CKO
, #8) of any CLB, plus the shortest possible interconnect delay, is always longer than
the Data In hold time requirement (T
CKDI
, #5) of any CLB on the same die.
