2-159
Speed Grade -70 -100 -125 Units
Description Symbol Min Max Min Max Min Max
Propagation Delays (Input)
Pad to Direct In (I) 3 T
PID
643ns
Pad to Registered In (Q) with latch transparent T
PTG
21 17 16 ns
Clock (IK) to Registered In (Q) 4 T
IKRI
5.5 4 3 ns
Set-up Time (Input)
Pad to Clock (IK) set-up time 1 T
PICK
20 17 16 ns
Propagation Delays (Output)
Clock (OK) to Pad (fast) 7 T
OKPO
13 10 9 ns
same (slew rate limited) 7 T
OKPO
33 27 24 ns
Output (O) to Pad (fast) 10 T
OPF
965ns
same (slew-rate limited) 10 T
OPS
29 23 20 ns
3-state to Pad begin hi-Z (fast) 9 T
TSHZ
887ns
same (slew-rate limited) 9 T
TSHZ
28 25 24 ns
3-state to Pad active and valid (fast) 8 T
TSON
14 12 11 ns
same (slew -rate limited) 8 T
TSON
34 29 27 ns
Set-up and Hold Times (Output)
Output (O) to clock (OK) set-up time 5 T
OOK
10 9 8 ns
Output (O) to clock (OK) hold time 6 T
OKO
00 0ns
Clock
Clock High time 11 T
IOH
54 3ns
Clock Low time 12 T
IOL
54 3ns
Max. flip-flop toggle rate F
CLK
70 100 125 MHz
Global Reset Delays (based on XC3042)
RESET Pad to Registered In (Q) 13 T
RRI
25 24 23 ns
RESET Pad to output pad (fast) 15 T
RPO
35 33 29 ns
(slew-rate limited) 15 T
RPO
53 45 42 ns
IOB Switching Characteristic Guidelines (continued)
Testing of the switching parameters is modeled after testing methods specified by MIL-M-38510/605. All devices are 100%
functionally tested. Since many internal timing parameters cannot be measured directly, they are derived from benchmark timing
patterns. The following guidelines reflect worst-case values over the recommended operating conditions. For more detailed, more
precise, and more up-to-date timing information, use the values provided by the XACT timing calculator and used in the simulator.
Notes: 1. Timing is measured at pin threshold, with 50 pF external capacitive loads (incl. test fixture). For larger capacitive loads,
see XAPP 024. Typical slew rate limited output rise/fall times are approximately four times longer.
2. Voltage levels of unused (bonded and unbonded) pads must be valid logic levels. Each can be configured with the
internal pull-up resistor or alternatively configured as a driven output or driven from an external source.
3. Input pad setup time and hold times are specified with respect to the internal clock (IK). To calculate system setup time,
subtract clock delay (clock pad to IK) from the specified input pad setup time value, but the subtracted value cannot be
less than zero (i.e., negative hold time). Negative hold time means that the delay in the input data is adequate for the
external system hold time to be zero, provided the input clock uses the Global signal distribution from pad to IK .
