NCV7342
www.onsemi.com
10
Table 6. CHARACTERISTICS
V
CC
= 4.5 V to 5.5 V; V
IO
= 2.8V to 5.5 V (Note 10); T
J
= −40 to +150°C; R
LT
= 60 W unless specified otherwise. On chip versions
without V
IO
pin reference voltage for all digital inputs and outputs is V
CC
instead of V
IO
.
Symbol UnitMaxTypMinConditionsParameter
BUS LINES (Pins CANH and CANL)
V
o(dom)
(CANL)
Dominant output voltage at pin
CANL
V
TxD
= 0 V 0.5 1.4 1.75 V
V
o(dif)
(bus_dom)
Differential bus output voltage
(V
CANH
− V
CANL
)
V
TxD
= 0 V; dominant;
45 W < R
LT
< 65 W
1.5 2.25 3.0 V
V
o(dif)
(bus_rec)
Differential bus output voltage
(V
CANH
− V
CANL
)
V
TxD
= V
IO
; recessive;
no load
−120 0 +50 mV
V
o(sym)
(bus_dom)
Bus output voltage symmetry
V
CANH
+ V
CANL
V
TxD
= 0 V 0.9 1.1 V
CC
I
o(sc)
(CANH)
Short circuit output current at pin
CANH
V
CANH
= 0 V; V
TxD
= 0 V
−90
−70 −40 mA
I
o(sc)
(CANL)
Short circuit output current at pin
CANL
V
CANL
= 36 V; V
TxD
= 0 V 40 70 100 mA
V
i(dif)
(th)
Differential receiver threshold
voltage
−12 V < V
CANL
< 12 V;
−12 V < V
CANH
< 12 V;
V
CC
= 4.75 V to 5.25 V
0.5 0.7 0.9 V
V
ihcm(dif)
(th)
Differential receiver threshold
voltage for high common−mode
−30 V < V
CANL
< 35 V;
−30 V < V
CANH
< 35 V;
V
CC
= 4.75 V to 5.25 V
0.40 0.7 1.0 V
V
i(dif)
(th)_STDBY
Differential receiver threshold
voltage in standby mode
−12 V < V
CANL
< 12 V;
−12 V < V
CANH
< 12 V;
V
CC
= 4.5 V to 5.5 V
0.4 0.8 1.15 V
R
i(cm)
(CANH)
Common−mode input resistance
at pin CANH
15 26 37
kW
R
i(cm)
(CANL)
Common−mode input resistance
at pin CANL
15 26 37
kW
R
i(cm)
(m)
Matching between pin CANH and
pin CANL common mode input
resistance
V
CANH
= V
CANL
−0.8 0 +0.8 %
R
i(dif)
Differential input resistance 25 50 75
kW
C
i(CANH)
Input capacitance at pin CANH V
TxD
= V
IO
; not tested 7.5 20 pF
C
i(CANL)
Input capacitance at pin CANL V
TxD
= V
IO
; not tested 7.5 20 pF
C
i(dif)
Differential input capacitance V
TxD
= V
IO
; not tested 3.75 10 pF
COMMON−MODE STABILIZATION (Pin V
SPLIT
) Only for NCV7342−0 version
V
SPLIT
Reference output voltage at pin
V
SPLIT
Normal mode;
−500 mA < I
SPLIT
< 500 mA
0.3 0.7 V
CC
V
SPLITo
Reference output voltage at pin
V
SPLIT
R
loadVsplit
> 1 MW
0.45 0.55 V
CC
I
SPLIT(i)
V
SPLIT
leakage current Standby mode −5 +5
mA
I
SPLIT(lim)
V
SPLIT
limitation current Normal mode 1.3 5 mA
V
IO
SUPPLY VOLTAGE (Pin V
IO
) Only for NCV7342−3 version
V
IO
Supply voltage on pin V
IO
2.8 5.5 V
I
IOS
Supply current on pin V
IO
in
standby mode
T
J
v 100°C (Note 11)
14
mA
10.Only version NCV7342−3 has V
IO
supply pin. In NCV7342−0 this supply is provided from V
CC
pin.
11. Not tested in production. Guaranteed by design and prototype evaluation.
12.In case V
IO
> V
CC
, the limit is V
IO
+ 0.3 V
NCV7342
www.onsemi.com
11
Table 6. CHARACTERISTICS
V
CC
= 4.5 V to 5.5 V; V
IO
= 2.8V to 5.5 V (Note 10); T
J
= −40 to +150°C; R
LT
= 60 W unless specified otherwise. On chip versions
without V
IO
pin reference voltage for all digital inputs and outputs is V
CC
instead of V
IO
.
Symbol UnitMaxTypMinConditionsParameter
V
IO
SUPPLY VOLTAGE (Pin V
IO
) Only for NCV7342−3 version
I
IONM
Supply current on pin V
IO
Normal mode
Dominant; V
TxD
= 0 V
Recessive; V
TxD
= V
IO
0.30
0.29
0.70
0.44
1.10
0.68
mA
V
UVDVIO
Undervoltage detection voltage on
V
IO
pin
1.3 2.7 V
THERMAL SHUTDOWN
T
J(SD)
Shutdown junction temperature junction temperature rising 160 180 200 °C
TIMING CHARACTERISTICS (See Figure 7 and 8)
t
d(TxD−BUSon)
Delay TxD to bus active C
i
= 100 pF between CANH to
CANL
60 ns
t
d(TxD−BUSoff)
Delay TxD to bus inactive C
i
= 100 pF between CANH to
CANL
30 ns
t
d(BUSon−RxD)
Delay bus active to RxD C
RxD
= 15 pF 60 ns
t
d(BUSoff−RxD)
Delay bus inactive to RxD C
RxD
= 15 pF 70 ns
t
pd_dr
Propagation delay TxD to RxD
dominant to recessive transition
See Figure 8
C
i
= 100 pF between CANH to
CANL, C
RxD
= 15 pF
50 100 230 ns
t
pd_rd
Propagation delay TxD to RxD
recessive to dominant transition
See Figure 8
C
i
= 100 pF between CANH to
CANL, C
RxD
= 15 pF
50 120 230 ns
t
d(stb−nm)
Delay standby mode to normal
mode
47
ms
t
Wake
Dominant time for wake−up via bus 0.5 2.1 5
ms
t
dwakerd
Delay to flag wake event
(recessive to dominant transitions)
See Figure 5
Valid bus wake−up event,
C
RxD
= 15 pF
1 3.5 10
ms
t
dwakedr
Delay to flag end of wake event
(dominant to recessive transition)
See Figure 5
Valid bus wake−up event,
C
RxD
= 15 pF
0.5 2.6 6
ms
t
Wake(RxD)
Minimum pulse width on RxD
See Figure 5
5 ms t
Wake
C
RxD
= 15 pF
0.5
ms
t
dom(TxD)
TxD dominant time for time out V
TxD
= 0 V 1.3 5 ms
t
dom(bus)
Bus dominant time out Standby mode 1.3 5 ms
10.Only version NCV7342−3 has V
IO
supply pin. In NCV7342−0 this supply is provided from V
CC
pin.
11. Not tested in production. Guaranteed by design and prototype evaluation.
12.In case V
IO
> V
CC
, the limit is V
IO
+ 0.3 V
Product parametric performance is indicated in the Electrical Characteristics for the listed test conditions, unless otherwise noted. Product
performance may not be indicated by the Electrical Characteristics if operated under different conditions.
NCV7342
www.onsemi.com
12
MEASUREMENT SET−UPS AND DEFINITIONS
NCV7342
GND
2
3
CANH
CANL
5
6
7
STB
8
RxD
4
TxD
1
1 nF
100 nF
+
1 nF
Transient
Generator
RB20121608
15 pF
5V
Figure 6. Test Circuit for Automotive Transients
8
NCV7342
GND
2
3
CANH
CANL
5
6
7
STB
RxD
4
TxD
1
100 nF
+5 V
47 uF
100 pF
RB20120816
15 pF
R
L
Figure 7. Test Circuit for Timing Characteristics
V
CC
V
IO
V
CC
V
IO

NCV7342D10R2G

Mfr. #:
Manufacturer:
ON Semiconductor
Description:
CAN Interface IC High Speed Low Pwr CAN Transceiver
Lifecycle:
New from this manufacturer.
Delivery:
DHL FedEx Ups TNT EMS
Payment:
T/T Paypal Visa MoneyGram Western Union

Products related to this Datasheet