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NCV7342D10R2G

P1-P3P4-P6P7-P9P10-P12P13-P15
NCV7342
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7
Over−temperature Detection
A thermal protection circuit protects the IC from damage
by switching off the transmitter if the junction temperature
exceeds a value of approximately 180°C. Because the
transmitter dissipates most of the power, the power
dissipation and temperature of the IC is reduced. All other
IC functions continue to operate. The transmitter off−state
resets when the temperature decreases below the shutdown
threshold and pin TxD goes High. The thermal protection
circuit is particularly needed in case of a bus line failure.
TxD Dominant Time−out Function
A TxD dominant time−out timer circuit prevents the bus
lines being driven to a permanent dominant state (blocking
all network communication), if pin TxD is forced
permanently Low by a hardware and/or software application
failure. The timer is triggered by a negative edge on pin TxD.
If the duration of the low−level on pin TxD exceeds the
internal timer value t
dom(TxD)
, the transmitter is disabled,
driving the bus into a recessive state. The timer is reset by a
positive edge on pin TxD.
This TxD dominant time−out time (t
dom(TxD)
) limits the
minimum possible bit rate to 8 kbps.
Bus Dominant Time−out Function
Bus dominant time−out timer is started in the standby
mode when CAN bus changes from recessive to dominant
state. If the dominant state on the bus is kept for longer time
than t
dom(bus)
, the RxD pin is released to High level. The
timer is reset when CAN bus changes from dominant to
recessive state. This feature prevents generating permanent
wake−up request by the bus clamped to the dominant level.
Fail Safe Features
A current−limiting circuit protects the transmitter output
stage from damage caused by an accidental short circuit to
either positive or negative supply voltage, although power
dissipation increases during this fault condition.
V
CC
supply dropping below V
UVVcc
undervoltage level
will force transceiver to switch into the standby mode. The
logic level on pin STB will be ignored as long as
undervoltage condition is not recovered. (NCV7342−3
version only)
V
IO
supply dropping below V
UVDVIO
undervoltage
detection level will cause the transceiver to disengage from
the bus (no bus loading) until the V
IO
voltage recovers.
(NCV7342−3 version only)
The pins CANH and CANL are protected against
automotive electrical transients (according to ISO 7637; see
Figure 6). Pins TxD and STB are pulled High internally
should the input become disconnected. Pins TxD, STB and
RxD will be floating, preventing reverse supply should the
V
CC
supply be removed.
NCV7342
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8
ELECTRICAL CHARACTERISTICS
Definitions
All voltages are referenced to GND (pin 2). Positive currents flow into the IC. Sinking current means the current is flowing
into the pin; sourcing current means the current is flowing out of the pin.
Table 4. ABSOLUTE MAXIMUM RATINGS
Symbol Parameter Conditions Min Max Unit
V
SUP
Supply voltage V
CC
, V
IO
−0.3 +6 V
V
CANH
DC voltage at pin CANH 0 < V
CC
< 5.5 V; no time limit −50 +50 V
V
CANL
DC voltage at pin CANL 0 < V
CC
< 5.5 V; no time limit −50 +50 V
V
CANH,Lmax
DC voltage at pin CANH and CANL during load dump
condition
0 < V
CC
< 5.5 V; less than
one second
− 58 V
V
SPLIT
DC voltage at V
SPLIT
pin (On NCV7342−0 version only) 0 < V
CC
< 5.5 V; no time limit −50 +50 V
V
IO
DC voltage at pin TxD, RxD, STB −0.3 +6 V
V
esd
Electrostatic discharge voltage at all pins according to
EIA−JESD22
(Note 2) −4 +4 kV
Standardized charged device model ESD pulses
according to ESD−STM5.3.1−1999
−750 +750 V
Electrostatic discharge voltage at CANH,CANL, V
SPLIT
pins according to EIA−JESD22
(Note 2) −8 +8 kV
Electrostatic discharge voltage at CANH, CANL pins
According to IEC 61000−4−2
(Note 3) −15 +15 kV
V
schaff
Transient voltage at CANH, CANL pins, See Figure 6 (Note 4) −150 +100 V
Latch−up Static latch−up at all pins (Note 5)
150
mA
T
stg
Storage temperature −55 +150 °C
T
amb
Ambient temperature −40 +125 °C
T
J
Maximum junction temperature −40 +170 °C
MSL Moisture Sensitivity Level SOIC 2 −
MSL Moisture Sensitivity Level DFN 1 −
T
SLD
Lead Temperature Soldering
Reflow (SMD Styles Only), Pb−Free Versions (Note 6)
260 °C
Stresses exceeding those listed in the Maximum Ratings table may damage the device. If any of these limits are exceeded, device functionality
should not be assumed, damage may occur and reliability may be affected.
2. Standardized human body model electrostatic discharge (ESD) pulses in accordance to EIA−JESD22. Equivalent to discharging a 100 pF
capacitor through a 1.5 kW resistor.
3. System human body model electrostatic discharge (ESD) pulses. Equivalent to discharging a 150 pF capacitor through a 330 W resistor
referenced to GND. Verified by external test house
4. Pulses 1, 2a,3a and 3b according to ISO 7637 part 3. Verification by external test house.
5. Static latch−up immunity: Static latch−up protection level when tested according to EIA/JESD78.
6. For information, please refer to our Soldering and Mounting Techniques Reference Manual, SOLDERRM/D
Table 5. THERMAL CHARACTERISTICS
Rating Symbol Value Unit
Thermal Characteristics, SOIC−8 (Note 7)
Thermal Resistance, Junction−to−Air, Free air, 1S0P PCB (Note 8)
Thermal Resistance, Junction−to−Air, Free air, 2S2P PCB (Note 9)
R
q
JA
R
q
JA
125
75
°C/W
°C/W
Thermal Characteristics, DFN−8, 3x3 mm (Note 7)
Thermal Resistance, Junction−to−Air, Free air, 1S0P PCB (Note 8)
Thermal Resistance, Junction−to−Air, Free air, 2S2P PCB (Note 9)
R
q
JA
R
q
JA
140
47
°C/W
°C/W
7. Refer to ELECTRICAL CHARACTERISTICS, RECOMMENDED OPERATING RANGES and/or APPLICATION INFORMATION for Safe
Operating parameters.
8. Values based on test board according to EIA/JEDEC Standard JESD51−3, signal layer with 10% trace coverage.
9. Values based on test board according to EIA/JEDEC Standard JESD51−7, signal layers with 10% trace coverage for the signal layer and
4 thermal vias connected between exposed pad and first inner Cu layer.
NCV7342
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9
Table 6. CHARACTERISTICS
V
CC
= 4.5 V to 5.5 V; V
IO
= 2.8V to 5.5 V (Note 10); T
J
= −40 to +150°C; R
LT
= 60 W unless specified otherwise. On chip versions
without V
IO
pin reference voltage for all digital inputs and outputs is V
CC
instead of V
IO
.
Symbol
Parameter Conditions Min Typ Max Unit
SUPPLY (Pin V
CC
)
I
CC
Supply current Dominant; V
TxD
= 0 V
Recessive; V
TxD
= V
IO
50
6.8
75
10
mA
I
CCS
0
Supply current in standby mode
for NCV7342−0
T
J
v 100°C (Note 11)
8 15
mA
I
CCS3
Supply current in standby mode
for NCV7342−3 including current
into V
IO
T
J
v 100°C (Note 11)
17
mA
V
UVVcc
Undervoltage detection voltage on
V
CC
pin (NCV7342−3 only)
3.5 4.5 V
TRANSMITTER DATA INPUT (Pin TxD)
V
IH
High−level input voltage Output recessive 2.0 6 V
V
IL
Low−level input voltage Output dominant −0.3 +0.8 V
I
IH
High−level input current V
TxD
= V
IO
−5 0 +5
mA
I
IL
Low−level input current V
TxD
= 0V −385 −200 −45
mA
C
i
Input capacitance Not tested 5 10 pF
TRANSMITTER MODE SELECT (Pin STB)
V
IH
High−level input voltage Standby mode 2.0 V
IO
+0.3
(Note 12)
V
V
IL
Low−level input voltage Normal mode −0.3 +0.8 V
I
IH
High−level input current V
STB
= V
IO
−5 0 +5
mA
I
IL
Low−level input current V
STB
= 0 V −10 −4 −1
mA
C
i
Input capacitance Not tested 5 10 pF
RECEIVER DATA OUTPUT (Pin RxD)
I
OH
High−level output current Normal mode
V
RxD
= V
IO
– 0.4 V
−1.2 −0.4
−0.1
mA
I
OL
Low−level output current V
RxD
= 0.4 V 1.5 6 12 mA
V
OH
High−level output voltage Standby mode
I
RxD
= −100 mA
V
IO
–
1.1
V
IO
–0.7
V
IO
– 0.4 V
BUS LINES (Pins CANH and CANL)
V
o(reces)
(norm)
Recessive bus voltage
on pins CANH and CANL
V
TxD
= V
IO
; no load; normal
mode
2.0 2.5 3.0 V
V
o(reces)
(stby)
Recessive bus voltage
on pins CANH and CANL
V
TxD
= V
IO
; no load; standby
mode
−100 0 +100 mV
I
o(reces)
(CANH)
Recessive output current at pin
CANH
−30 V < V
CANH
< 35 V;
0 V < V
CC
< 5.5 V
−2.5 +2.5 mA
I
o(reces)
(CANL)
Recessive output current at pin
CANL
−30 V < V
CANL
< 35 V;
0 V <V
CC
< 5.5 V
−2.5 +2.5 mA
I
LI(CANH)
Input leakage current to pin CANH 0W < R(V
CC
to GND) < 1 MW
0W < R(V
IO
to GND) < 1 MW
V
CANL
= V
CANH
= 5 V (Note 10)
−10 0 +10
mA
I
LI(CANL)
Input leakage current to pin CANL −10 0 +10
mA
V
o(dom)
(CANH)
Dominant output voltage at pin
CANH
V
TxD
= 0 V 3.0 3.6 4.25 V
10.Only version NCV7342−3 has V
IO
supply pin. In NCV7342−0 this supply is provided from V
CC
pin.
11. Not tested in production. Guaranteed by design and prototype evaluation.
12.In case V
IO
> V
CC
, the limit is V
IO
+ 0.3 V
P1-P3P4-P6P7-P9P10-P12P13-P15

NCV7342D10R2G

Mfr. #:
Buy NCV7342D10R2G
Manufacturer:
ON Semiconductor
Description:
CAN Interface IC High Speed Low Pwr CAN Transceiver
Lifecycle:
New from this manufacturer.
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