FUNCTIONAL BLOCK DIAGRAM
REV.
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a
LC
2
MOS
(8+4) Loading Dual 12-Bit DAC
AD7537
One Technology Way, P.O. Box 9106, Norwood, MA 02062-9106, U.S.A.
Tel: Fax:
FEATURES
Two 12-Bit DACs in One Package
DAC Ladder Resistance Matching: 0.5%
Space Saving Skinny DIP and Surface Mount Packages
4-Quadrant Multiplication
Low Gain Error (1 LSB max Over Temperature)
Byte Loading Structure
Fast Interface Timing
APPLICATIONS
Automatic Test Equipment
Programmable Filters
Audio Applications
Synchro Applications
Process Control
GENERAL DESCRIPTION
The AD7537 contains two 12-bit current output DACs on one
monolithic chip. A separate reference input is provided for each
DAC. The dual DAC saves valuable board space, and the
monolithic construction ensures excellent thermal tracking.
Both DACs are guaranteed 12-bit monotonic over the full tem-
perature range.
The AD7537 has a 2-byte (8 LSBs, 4 MSBs) loading structure.
It is designed for right-justified data format. The control signals
for register loading are A0, A1,
CS, WR and UPD. Data is
loaded to the input registers when
CS and WR are low. To
transfer this data to the DAC registers,
UPD must be taken low
with
WR.
Added features on the AD7537 include an asynchronous
CLR
line which is very useful in calibration routines. When this is
taken low, all registers are cleared. The double buffering of the
data inputs allows simultaneous update of both DACs. Also,
each DAC has a separate AGND line. This increases the device
versatility; for instance one DAC may be operated with
AGND biased while the other is connected in the standard
configuration.
The AD7537 is manufactured using the Linear Compatible
CMOS (LC
2
MOS) process. It is speed compatible with most
microprocessors and accepts TTL, 74HC and 5 V CMOS logic
level inputs.
PRODUCT HIGHLIGHTS
1. DAC to DAC Matching:
Since both DACs are fabricated on the same chip, precise
matching and tracking is inherent. Many applications which
are not practical using two discrete DACs are now possible.
Typical matching: 0.5%.
2. Small Package Size:
The AD7537 is packaged in small 24-pin 0.3" DIPs and in
28-terminal surface mount packages.
3. Wide Power Supply Tolerance:
The device operates on a +12 V to +15 V V
DD
, with ±10%
tolerance on this nominal figure. All specifications are
guaranteed over this range.
A
781/329-4700 781/461-3113
AD7537* PRODUCT PAGE QUICK LINKS
Last Content Update: 02/23/2017
COMPARABLE PARTS
View a parametric search of comparable parts.
DOCUMENTATION
Application Notes
AN-206: CMOS Multiplying DAC Based Panning Circuit
Provides Almost Constant Output Power
AN-209: 8th Order Programmable Low-Pass Analog Filter
Using Dual 12-Bit CMOS Multiplying DACs
AN-225: 12-Bit Voltage-Output DACs for Single-Supply 5V
and 12V Systems
Data Sheet
AD7537: LC
2
MOS (8+4) Loading, Dual 12-Bit DAC Data
Sheet
AD7537: Military Data Sheet
REFERENCE MATERIALS
Solutions Bulletins & Brochures
Digital to Analog Converters ICs Solutions Bulletin
DESIGN RESOURCES
AD7537 Material Declaration
PCN-PDN Information
Quality And Reliability
Symbols and Footprints
DISCUSSIONS
View all AD7537 EngineerZone Discussions.
SAMPLE AND BUY
Visit the product page to see pricing options.
TECHNICAL SUPPORT
Submit a technical question or find your regional support
number.
DOCUMENT FEEDBACK
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REV.
–2–
AD7537–SPECIFICATIONS
(V
DD
= +12 V to +15 V, 10%, V
REFA
= V
REFB
= 10 V; I
OUTA
= AGND = 0 V,
I
OUTB
= AGNDB = 0 V. All specifications T
MIN
to T
MAX
unless otherwise noted.)
AC PERFORMANCE CHARACTERISTICS
These characteristics are included for Design Guidance only and are not subject to test.
(V
DD
= +12 V to +15 V; V
REFA
= V
REFB
= +10 V; I
OUTA
= AGNDA = 0 V, I
OUTB
= AGNDB = 0 V. Output Amplifiers are AD644 except where noted.)
Parameter T
A
= +25CT
A
= T
MIN
, T
MAX
Units Test Conditions/Comments
Output Current Settling Time 1.5 μs max To 0.01% of full-scale range. I
OUT
load = 100 Ω, C
EXT
= 13 pF.
DAC output measured from falling edge of
WR.
Typical Value of Settling Time is 0.8 μs.
Digital-to-Analog Glitch lmpulse 7 nV-s typ Measured with V
REFA
= V
REFB
= 0 V. I
OUTA
, I
OUTB
load = 100 Ω,
C
EXT
= 13 pF. DAC registers alternately loaded with all 0s and all 1s.
AC Feedthrough
4
V
REFA
to I
OUTA
–70 –65 dB max V
REFA
, V
REFB
= 20 V p-p 10 kHz sine wave.
V
REFB
to I
OUTB
–70 –65 dB max DAC registers loaded with all 0s.
Power Supply Rejection
ΔGain/ΔV
DD
±0.01 ±0.02 % per % max ΔV
DD
= V
DD
max – V
DD
min
Output Capacitance
C
OUTA
70 70 pF max DAC A, DAC B loaded with all 0s
C
OUTB
70 70 pF max
C
OUTA
140 140 pF max DAC A, DAC B loaded with all 1s
C
OUTB
140 140 pF max
Channel-to-Channel Isolation
V
REFA
to I
OUTB
–84 dB typ V
REFA
= 20 V p-p 10 kHz sine wave, V
REFB
= 0 V.
Both DACs loaded with all 1s.
V
REFB
to I
OUTA
–84 dB typ V
REFB
= 20 V p-p 10 kHz sine wave, V
REFA
= 0 V.
Both DACs loaded with all 1s.
Digital Crosstalk 7 nV-s typ Measured for a Code Transition of all 0s to all 1s.
I
OUTA
, I
OUTB
load = 100 Ω, C
EXT
= 13 pF.
Output Noise Voltage Density 25 nV/
Hz typ Measured between R
FBA
and I
OUTA
or R
FBB
and I
OUTB.
(10 Hz–100 kHz) Frequency of measurement is 10 Hz–100 kHz.
Total Harmonic Distortion –82 dB typ V
IN
= 6 V rms, 1 kHz. Both DACs loaded with all 1s.
NOTES
1
Temperature range as follows: J, K, L Versions: –40°C to +85°C;
A, B, C Versions: –40°C to +85°C;
S, T, U Versions: –55°C to +125°C
Specifications subject to change without notice.
2
Sample tested at +25°C to ensure compliance.
3
Functional at V
DD
= 5 V, with degraded specifications.
4
Pin 12 (DGND) on ceramic DIPs is connected to lid.
J, A K, B L, C S T U
Parameter Versions Versions Versions Version Version Version Units Test Conditions/Comments
ACCURACY
Resolution 12 12 12 12 12 12 Bits
Relative Accuracy ±1 ±1/2 ± 1/2 ±1 ±1/2 ± 1/2 LSB max
Differential Nonlinearity ±1 ±1 ±1 ±1 ±1 ±1 LSB max All grades guaranteed mono-
tonic over temperature.
Gain Error ±6 ±3 ±1 ±6 ±3 ±2 LSB max Measured using R
FBA
, R
FBB
.
Both DAC registers loaded
with all 1s.
Gain Temperature Coefficient
2
;
ΔGain/ΔTemperature ±5 ±5 ±5 ±5 ±5 ±5 ppm/°C max Typical value is 1 ppm/°C
Output Leakage Current
I
OUTA
+25°C 10 10 10 10 10 10 nA max DAC A Register loaded
T
MIN
to T
MAX
150 150 150 250 250 250 nA max with all 0s
I
OUTB
+25°C 10 10 10 10 10 10 nA max DAC B Register loaded
T
MIN
to T
MAX
150 150 150 250 250 250 nA max with all 0s
REFERENCE INPUT
Input Resistance 999999kΩ min Typical Input Resistance = 14 kΩ
20 20 20 20 20 20 kΩ max
V
REFA
, V
REFB
Input Resistance Match ± 3 ± 3 ± 1 ± 3 ± 3 ± 1 % max Typically ±0.5%
DIGITAL INPUTS
V
IH
(lnput High Voltage) 2.4 2.4 2.4 2.4 2.4 2.4 V min
V
IIL
(Input Low Voltage) 0.8 0.8 0.8 0.8 0.8 0.8 V max
I
IN
(Input Current)
+25°C ±1 ±1 ±1 ±1 ±1 ±1 μA max V
IN
= V
DD
T
MIN
to T
MAX
±10 ±10 ±10 ±10 ±10 ±10 μA max
C
IN
(lnput Capacitance)
2
10 10 10 10 10 10 pF max
POWER SUPPLY
3
V
DD
10.8/16.5 10.8/16.5 10.8/16.5 10.8/16.5 10.8/16.5 10.8/16.5 V min/V max
I
DD
222222mA max
A

AD7537KRZ

Mfr. #:
Manufacturer:
Analog Devices Inc.
Description:
Digital to Analog Converters - DAC LC2MOS Loading Dual 12-Bit
Lifecycle:
New from this manufacturer.
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