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AD7537KRZ

P1-P3P4-P6P7-P9P10-P11
AD7537
REV.
–3–
TIMING CHARACTERISTICS
Limit at Limit at
Limit at T
A
= –40ⴗCT
A
= +55ⴗC
Parameter T
A
= +25ⴗC to +85ⴗC to +125ⴗC Units Test Conditions/Comments
t
1
15 15 30 ns min Address Valid to Write Setup Time
t
2
15 15 25 ns min Address Valid to Write Hold Time
t
3
60 80 80 ns min Data Setup Time
t
4
25 25 25 ns min Data Hold Time
t
5
0 0 0 ns min Chip Select or Update to Write Setup Time
t
6
0 0 0 ns min Chip Select or Update to Write Hold Time
t
7
80 80 100 ns min Write Pulse Width
t
8
80 80 100 ns min Clear Pulse Width
Specifications subject to change without notice.
ABSOLUTE MAXIMUM RATINGS*
(T
A
= +25°C unless otherwise stated)
V
DD
to DGND . . . . . . . . . . . . . . . . . . . . . . . . . .–0.3 V, +17 V
V
REFA
, V
REFB
to AGNDA, AGNDB . . . . . . . . . . . . . . . . ±25 V
V
RFBA
, V
RFBB
to AGNDA, AGNDB . . . . . . . . . . . . . . . . ±25 V
Digital Input Voltage to DGND . . . . . . . –0.3 V, V
DD
+0.3 V
I
OUTA
, I
OUTB
to DGND . . . . . . . . . . . . . . –0.3 V, V
DD
+0.3 V
AGNDA, AGNDB to DGND . . . . . . . . . –0.3 V, V
DD
+0.3 V
Power Dissipation (Any Package)
To +75°C . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 450 mW
Derates Above +75°C . . . . . . . . . . . . . . . . . . . . . 6 mW/°C
Operating Temperature Range
Commercial Plastic (J, K, L Versions) . . . . –40°C to +85°C
Industrial Hermetic (A, B, C Versions) . . . –40°C to +85°C
Extended Hermetic (S, T, U Versions) . . –55°C to +125°C
Storage Temperature . . . . . . . . . . . . . . . . –65°C to +150°C
Lead Temperature (Soldering, 10 sec) . . . . . . . . . . . . +300°C
*Stresses above those listed under “Absolute Maximum Ratings” may cause
permanent damage to the device. This is a stress rating only and functional
operation of the device at these or any other conditions above those indicated in
the operational sections of this specification is not implied. Exposure to absolute
maximum rating conditions for extended periods may affect device reliability.
WARNING!
ESD SENSITIVE DEVICE
CAUTION
ESD (electrostatic discharge) sensitive device. Electrostatic charges as high as 4000 V readily
accumulate on the human body and test equipment and can discharge without detection.
Although the AD7537 features proprietary ESD protection circuitry, permanent damage may
occur on devices subjected to high energy electrostatic discharges. Therefore, proper ESD
precautions are recommended to avoid performance degradation or loss of functionality.
Figure 1. Timing Diagram
(V
DD
= +10.8 V to +16.5 V, V
REFA
= V
REFB
= +10 V; I
OUTA
= AGNDA = 0 V, I
OUTB
= AGNDB = 0 V.)
A
AD7537
REV.
–4–
PIN FUNCTION DESCRIPTION
PIN MNEMONIC DESCRIPTION
1 AGNDA Analog Ground for DAC A.
2I
OUTA
Current output terminal of DAC A.
3R
FBA
Feedback resistor for DAC A.
4V
REFA
Reference input to DAC A.
5
CS Chip Select Input Active low.
6–14 DB0–DB7 Eight data inputs, DB0–DB7.
12 DGND Digital Ground.
15 A0 Address Line 0.
16 A1 Address Line 1.
17
CLR Clear Input. Active low. Clears all
registers.
18
WR Write Input. Active low.
19
UPD Updates DAC Registers from inputs
registers.
20 V
DD
Power supply input. Nominally +12 V
to +15 V, with ±10% tolerance.
21 V
REFB
Reference input to DAC B.
22 R
FBB
Feedback resistor for DAC B.
23 I
OUTB
Current output terminal of DAC B.
24 AGNDB Analog Ground for DAC B.
PLCC
PIN CONFIGURATIONS
CIRCUIT INFORMATION – D/A SECTION
The AD7537 contains two identical 12-bit multiplying D/A
converters. Each DAC consists of a highly stable R-2R ladder
and 12 N-channel current steering switches. Figure 2 shows a
simplified D/A circuit for DAC A. In the R-2R ladder, binary
weighted currents are steered between I
OUTA
and AGNDA. The
current flowing in each ladder leg is constant, irrespective of
switch state. The feedback resistor R
FBA
is used with an op amp
(see Figures 4 and 5) to convert the current flowing in I
OUTA
to
a voltage output.
Figure 2. Simplified Circuit Diagram for DAC A
EQUIVALENT CIRCUIT ANALYSIS
Figure 3 shows the equivalent circuit for one of the D/A con-
verters (DAC A) in the AD7537. A similar equivalent circuit
can be drawn for DAC B.
C
OUT
is the output capacitance due to the N-channel switches
and varies from about 50 pF to 150 pF with digital input code.
The current source I
LKG
is composed of surface and junction
leakages and approximately doubles every 10°C. R
0
is the
equivalent output resistance of the device which varies with
input code.
DIGITAL CIRCUIT INFORMATION
The digital inputs are designed to be both TTL and 5 V CMOS
compatible. All logic inputs are static protected MOS gates with
typical input currents of less than 1 nA.
Table I. AD7537 Truth Table
CLR UPD CS WR A1 A0 FUNCTION
1 1 1 X X X No Data Transfer
1 1 X 1 X X No Data Transfer
0 X X X X X All Registers Cleared
1 1 0 0 0 0 DAC A LS Input Register
Loaded with DB7–DB0 (LSB)
1 1 0 0 0 1 DAC A MS Input Register
Loaded with DB3 (MSB)–DB0
1 1 0 0 1 0 DAC B LS Input Register
Loaded with DB7–DB0 (LSB)
1 1 0 0 1 1 DAC B MS Input Register
Loaded with DB3 (MSB)–DB0
1 0 1 0 X X DAC A, DAC B Registers
Updated Simultaneously from
Input Registers
1 0 0 0 X X DAC A, DAC B Registers are
Transparent
NOTES: X = Don’t care
Figure 3. Equivalent Analog Circuit for DAC A
A
PDIP and SOIC
(PDIP)
AD7537
REV.
–5–
UNIPOLAR BINARY OPERATION
(2-QUADRANT MULTIPLICATION)
Figure 4 shows the circuit diagram for unipolar binary opera-
tion. With an ac input, the circuit performs 2-quadrant multipli-
cation. The code table for Figure 4 is given in Table II.
Operational amplifiers A1 and A2 can be in a single package
(AD644, AD712) or separate packages (AD544, AD711,
AD OP27). Capacitors C1 and C2 provide phase compensation
to help prevent overshoot and ringing when high-speed op amps
are used.
For zero offset adjustment, the appropriate DAC register is
loaded with all 0s and amplifier offset adjusted so that V
OUTA
or
V
OUTB
is 0 V. Full-scale trimming is accomplished by loading
the DAC register with all 1s and adjusting R1 (R3) so that
V
OUTA
(V
OUTB
) = –V
IN
(4095/4096). For high temperature op-
eration, resistors and potentiometers should have a low Tem-
perature Coefficient. In many applications, because of the
excellent Gain T.C. and Gain Error specifications of the
AD7537, Gain Error trimming is not necessary. In fixed refer-
ence applications, full scale can also be adjusted by omitting R1,
R2, R3, R4 and trimming the reference voltage magnitude.
Figure 4. AD7537 Unipolar Binary Operation
Table II. Unipolar Binary Code Table for
Circuit of Figure 4
Binary Number in
DAC Register Analog Output,
MSB LSB V
OUTA
or V
OUTB
1111 1111 1111
−V
IN
4095
4096
⎛
⎝
⎜
⎞
⎠
⎟
1000 0000 0000
−V
IN
2048
4096
⎛
⎝
⎜
⎞
⎠
⎟
=−
1
2
V
IN
0000 0000 0001
−V
IN
1
4096
⎛
⎝
⎜
⎞
⎠
⎟
0000 0000 0000 0 V
BIPOLAR OPERATION
(4-QUADRANT MULTIPLICATION)
The recommended circuit diagram for bipolar operation is
shown in Figure 5. Offset binary coding is used.
With the appropriate DAC register loaded to 1000 0000 0000,
adjust R1 (R3) so that V
OUTA
(V
OUTB
) = 0 V. Alternatively, R1,
R2 (R3, R4) may be omitted and the ratios of R6, R7 (R9, 10)
varied for V
OUTA
(V
OUTB
) = 0 V. Full-scale trimming can be ac-
complished by adjusting the amplitude of V
IN
or by varying the
value of R5 (R8).
If R1, R2 (R3, R4) are not used, then resistors R5, R6, R7 (R8,
R9, R10) should be ratio matched to 0.01% to ensure gain error
performance to the data sheet specification. When operating
over a wide temperature range, it is important that the resistors
be of the same type so that their temperature coefficients match.
The code table for Figure 5 is given in Table III.
Figure 5. Bipolar Operation (Offset Binary Coding)
Table III. Bipolar Code Table for Offset Binary
Circuit of Figure 5
Binary Number in
DAC Register Analog Output,
MSB LSB V
OUTA
or V
OUTB
1111 1111 1111
+V
IN
2047
2048
⎛
⎝
⎜
⎞
⎠
⎟
1000 0000 0001
+V
IN
1
2048
⎛
⎝
⎜
⎞
⎠
⎟
1000 0000 0000 0 V
0111 1111 1111
−V
IN
1
2048
⎛
⎝
⎜
⎞
⎠
⎟
0000 0000 0000
−V
IN
2048
2048
⎛
⎝
⎜
⎞
⎠
⎟
=−V
IN
Applications–
A
P1-P3P4-P6P7-P9P10-P11

AD7537KRZ

Mfr. #:
Buy AD7537KRZ
Manufacturer:
Analog Devices Inc.
Description:
Digital to Analog Converters - DAC LC2MOS Loading Dual 12-Bit
Lifecycle:
New from this manufacturer.
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