AD7537
REV.
–6–
SEPARATE AGND PINS
The DACs in the AD7537 have separate AGND lines taken to
pins AGNDA and AGNDB on the package. This increases the
applications versatility of the part. Figure 6 is an example of
this. DAC A is connected in standard fashion as a program-
mable attenuator. AGNDA is at ground potential. DAC B is op-
erating with AGND B biased to +5 V by the AD584. This gives
an output range of +5 V to +10 V.
Figure 6. AD7537 DACs Used in Different Modes
PROGRAMMABLE OSCILLATOR
Figure 7 shows a conventional state variable oscillator in which
the AD7537 controls the programmable integrators. The fre-
quency of oscillation is given by:
f =
1
2π
R6
R5
×
1
C1×C2× R
EQ1
× R
EQ2
where R
EQ1
and R
EQ2
are the equivalent resistances of the
DACs. The same digital code is loaded into both DACs.
If C1 = C2 and R5 = R6, the expression reduces to
f =
1
2π
×
1
C
1
R
EQ1
× R
EQ2
Since
R
EQ
=
2
n
× R
LAD
N
, (R
LAD
= DAC ladder resistance).
f =
1
2π
×
1
C
(N /2
n
)
2
R
LAD1
× R
LAD2
=
1
2π
×
D
C
1
R
LAD1
× R
LAD2
D =
N
2
n
=
1
2π
×
D
C × R
LAD m
where m is the DAC ladder resistance mismatch ratio, typically
1.005.
With the values shown in Figure 7, the output frequency varies
from 0 Hz to 1.38 kHz. The amplitude of the output signal at
the A3 output is 10 V peak-to-peak and is constant over the
entire frequency span.
Figure 7. Programmable State Variable Oscillator
A
AD7537
REV.
–7–
APPLICATION HINTS
Output Offset: CMOS D/A converters in circuits such as Fig-
ures 4 and 5 exhibit a code dependent output resistance which
in turn can cause a code dependent error voltage at the output
of the amplifier. The maximum amplitude of this error, which
adds to the D/A converter nonlinearity, depends on V
OS
, where
V
OS
is the amplifier input offset voltage. To maintain specified
operation, it is recommended that V
OS
be no greater than
(25 10
–6
) (V
REF
) over the temperature range of operation.
Suitable op amps are the AD711C and its dual version, the
AD712C. These op amps have a wide bandwidth and high slew
rate and are recommended for wide bandwidth ac applications.
AD711/AD712 settling time to 0.01% is typically 3 μs.
Temperature Coefficients: The gain temperature coefficient
of the AD7537 has a maximum value of 5 ppm/°C and typical
value of 1 ppm/°C. This corresponds to worst case gain shifts of
2 LSBs and 0.4 LSBs respectively over a 100°C temperature
range. When trim resistors R1 (R3) and R2 (R4) are used to ad-
just full scale range as in Figure 4, the temperature coefficient of
R1 (R3) and R2 (R4) should also be taken into account. For
further information see “Gain Error and Gain Temperature Co-
efficient of CMOS Multiplying DACs”, Application Note, Pub-
lication Number E630c-5-3/86 available from Analog Devices.
High Frequency Considerations: AD7537 output capaci-
tance works in conjunction with the amplifier feedback resis-
tance to add a pole to the open loop response. This can cause
ringing or oscillation. Stability can be restored by adding a
phase compensation capacitor in parallel with the feedback re-
sistor. This is shown as C1 and C2 in Figures 4 and 5.
Feedthrough: The dynamic performance of the AD7537 de-
pends upon the gain and phase stability of the output amplifier,
together with the optimum choice of PC board layout and de-
coupling components. A suggested printed circuit layout for
Figure 4 is shown in Figure 8 which minimizes feedthrough
from V
REFA
, V
REFB
to the output in multiplying applications.
Figure 8. Suggested Layout for AD7537
MICROPROCESSOR INTERFACING
The byte loading structure of the AD7537 makes it very easy to
interface the device to any 8-bit microprocessor system. Figures
9 and 10 show two interfaces: one for the MC6809 and the
other for the MC68008. Figure 11 shows how an AD7537 sys-
tem can be easily expanded by tying all the
UPD lines together
and using a single decoder output to control these. This ex-
panded system is shown using a Z80 microprocessor but it is
just as easily configured using any other 8-bit microprocessor
system. Note how the system shown in Figure 11 produces 4
analog outputs with a minimum amount of hardware.
Figure 9. AD7537–MC6809 Interface
Figure 10. AD7537–MC68008 Interface
Figure 11. Expanded AD7537 System
A
AD7537
–8– REV. A
OUTLINE DIMENSIONS
Figure 12. 24-Lead Plastic Dual In-Line Package [PDIP]
Narrow Body
(N-24-1)
Dimensions shown in inches and (millimeters)
Figure 16. 28-Lead Plastic Leaded Chip Carrier [PLCC]
(P-28)
Dimensions shown in inches and (millimeters)
CONTROLLING DIMENSIONS ARE IN INCHES; MILLIMETER DIMENSIONS
(IN PARENTHESES) ARE ROUNDED-OFF INCH EQUIVALENTS FOR
REFERENCE ONLY AND ARE NOT APPROPRIATE FOR USE IN DESIGN.
CORNER LEADS MAY BE CONFIGURED AS WHOLE OR HALF LEADS.
COMPLIANT TO JEDEC STANDARDS MS-001
071006-A
0.022 (0.56)
0.018 (0.46)
0.014 (0.36)
0.150 (3.81)
0.130 (3.30)
0.115 (2.92)
0.070 (1.78)
0.060 (1.52)
0.045 (1.14)
24
1
12
13
0.100 (2.54)
BSC
1.280 (32.51)
1.250 (31.75)
1.230 (31.24)
0.210 (5.33)
MAX
SEATING
PLANE
0.015
(0.38)
MIN
0.005 (0.13)
MIN
0.280 (7.11)
0.250 (6.35)
0.240 (6.10)
0.060 (1.52)
MAX
0.430 (10.92)
MAX
0.014 (0.36)
0.010 (0.25)
0.008 (0.20)
0.325 (8.26)
0.310 (7.87)
0.300 (7.62)
0.015 (0.38)
GAUGE
PLANE
0.195 (4.95)
0.130 (3.30)
0.115 (2.92)
COMPLIANT TO JEDEC STANDARDS MO-047-AB
CONTROLLING DIMENSIONS ARE IN INCHES; MILLIMETER DIMENSIONS
(IN PARENTHESES) ARE ROUNDED-OFF INCH EQUIVALENTS FOR
REFERENCE ONLY AND ARE NOT APPROPRIATE FOR USE IN DESIGN.
4
5
26
25
11
12
19
18
TOP VIEW
(PINS DOWN)
SQ
0.456 (11.582)
0.450 (11.430)
0.050
(1.27)
BSC
0.048 (1.22)
0.042 (1.07)
0.048 (1.22)
0.042 (1.07)
0.495 (12.57)
0.485 (12.32)
SQ
0.021 (0.53)
0.013 (0.33)
0.430 (10.92)
0.390 (9.91)
0.032 (0.81)
0.026 (0.66)
0.120 (3.04)
0.090 (2.29)
0.056 (1.42)
0.042 (1.07)
0.020 (0.51)
MIN
0.180 (4.57)
0.165 (4.19)
BOTTOM
VIEW
(PINS UP)
0.045 (1.14)
0.025 (0.64)
R
PIN 1
IDENTIFIER
042508-A

AD7537KRZ

Mfr. #:
Manufacturer:
Analog Devices Inc.
Description:
Digital to Analog Converters - DAC LC2MOS Loading Dual 12-Bit
Lifecycle:
New from this manufacturer.
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