ISL6540ACRZ Datasheet ISL6540ACRZ-T, ISL6540AIRZ, ISL6540AIRZ-T | P13-P15

FN6288.5

October 7, 2008

point varies mainly due to the MOSFETs r

DS(ON)

variations

and system noise. To avoid overcurrent tripping in the

normal operating load range, find the R

HSOC

and/or R

LSOC

resistor from the previous detailed equations with:

1. Maximum r

DS(ON)

at the highest junction temperature.

2. Minimum I

LSOC

and/or I

HSOC

from specification table on

page 8.

3. Determine the overcurrent trip point greater than the

maximum output continuous current at maximum

inductor ripple current.

Frequency Programming

By tying a resistor to GND from FS pin, the switching

frequency can be set between 250kHz and 2MHz.

Oscillator/VFF

The Oscillator is a triangle waveform, providing for leading

and falling edge modulation. The bottom of the oscillator

waveform is set at 1.0V. The ramp's peak-to-peak amplitude

is determined from the voltage on the VFF (Voltage

Feed-Forward) pin. See Equation 6:

An internal RC filter of 233kΩ and 2pF (341kHz) provides

filtering of the VFF voltage. An external RC filter may be

required to augment this filter in the event that it is

insufficient to prevent noise injection or control loop

interactions. Voltages below 2.9V on the VFF pin may result

in undesirable operation due to extremely small peak to

peak oscillator waveforms. The oscillator waveform should

not exceed VCC -1.0V. For high VFF voltages the

internal/external 5.5V linear regulator should be used. 5.5V

on VCC provides sufficient headroom for 100% duty cycle

operation when using the maximum VFF voltage of 22V. In

the event of sustained 100% duty cycle operation, defined as

32-clock cycles where no LG pulse is detected, LG will be

pulsed on to refresh the design’s bootstrap capacitor.

Internal Series Linear Regulator

The VIN pin is connected to PVCC with a 2Ω internal series

linear regulator, which is internally compensated. The

external series linear regulator option should be used for

applications requiring pass elements of less than 2Ω. When

using the internal regulator, the LIN_DRV pin should be

connected directly to GND. The PVCC and VIN pins should

have a bypass capacitor (at least 10µF on PVCC is required)

connected to PGND. For proper operation the PVCC

capacitor must be within 150 mils of the PVCC and the

PGND pins, and be connected to these pins with dedicated

traces. The internal series linear regulator’s input (VIN) can

range between 3.3V to 20V ±10%. The internal linear

regulator is to provide power for both the internal MOSFET

drivers through the PVCC pin and the analog circuitry

through the VCC pin. The VCC pin should be connected to

the PVCC pin with an RC filter to prevent high frequency

driver switching noise from entering the analog circuitry.

When VIN drops below 5.5V, the pass element will saturate;

PVCC will track VIN, minus the dropout of the linear

regulator: PVCC = VIN-2xI

VIN

. When used with an external

5V supply, the VIN pin should be tied directly to PVCC.

At start-up (PVCC = 0V and VIN = 0V) the DV/DT on VIN

should be kept below 1V/µs to prevent electrical overstress

on PVCC. Care should be taken to keep the DV/DT on VIN

below 0.05V/µs if the initial steady state voltage on PVCC is

above 2.0V, as electrical overstress on PVCC is otherwise

possible.

External Series Linear Regulator

The LIN_DRV pin provides sinking drive capability for an

external pass element linear regulator controller. The

external linear options are especially useful when the

ΔVosc 0.16 VFF•=

(EQ. 6)

200k

400k

600k

800k

300k

FIGURE 4. R

RESISTANCE vs FREQUENCY

FREQUENCY (Hz)

RESISTANCE (kΩ)

Fs Hz[]1.178

×10 R

Ω[]

0.973–

TO GND)•≈

(EQ. 7)

ISL6540A

FN6288.5

October 7, 2008

internal linear dropout is too large for a given application.

When using the external linear regulator option, the

LIN_DRV pin should be connected to the gate of a PMOS

device, and a resistor should be connected between its gate

and source. A resistor and a capacitor should be connected

from gate-to-source to compensate the control loop. A PNP

device can be used instead of a PMOS device in which case

the LIN_DRV pin should be connected to the base of the

PNP pass element. The sinking capability of the LIN_DRV

pin is 5mA, and should not be exceeded if using an external

resistor for a PMOS device. The designer should take care

in designing a stable system when using external pass

elements. The VCC pin should be connected to the PVCC

pin with an RC filter to prevent high frequency driver

switching noise from entering the analog circuitry.

High Speed MOSFET Gate Driver

The integrated driver has similar drive capability and

features to Intersil's ISL6605 stand alone gate driver. The

PWM tri-state feature helps prevent a negative transient on

the output voltage when the output is being shut down. This

eliminates the Schottky diode that is used in some systems

for protecting the microprocessor from

reversed-output-voltage damage. See the ISL6605

datasheet for specification parameters that are not defined in

the current ISL6540A “Electrical Specifications” table on

page 6.

A 1Ω to 2Ω resistor is recommended to be in series with the

bootstrap diode when using VCCs above 5.0V to prevent the

bootstrap capacitor from overcharging due to the negative

swing of the trailing edge of the phase node.

Margining Control

When the MAR_CTRL is pulled high or low, the positive or

negative margining functionality is respectively enabled.

When MAR_CTRL is left floating, the function is disabled.

Upon UP margining, an internal buffer drives the OFS- pin

from VCC to maintain OFS+ at 0.591V. The resistor divider,

MARG

and R

OFS+

, causes the voltage at OFS- to be

increased. Similarly, upon DOWN margining, an internal

buffer drives the OFS+ pin from VCC to maintain OFS- at

0.591V. The resistor divider, R

MARG

and R

OFS-

, causes the

voltage at OFS+ to be increased. In both modes, the voltage

difference between OFS+ and OFS- is then sensed with an

instrumentation amplifier and is converted to the desired

margining voltage by a 5:1 ratio. The maximum designed

margining range of the ISL6540A is ±200mV, this sets the

MINIMUM value of R

OFS+

or R

OFS-

at approximately 5.9k

for an R

MARG

of 10k for a MAXIMUM of 1V across R

MARG

The OFS pins are completely independent and can be set to

different margining levels. The maximum usable reference

voltage for the ISL6540A is VCC-1.8V, and should not be

exceeded when using the margining functionality, for

example: V

REF_MARG

< VCC - 1.8V, as shown in

Equation 8:

An alternative calculation provides for a desired percentage

change in the output voltage when using the internal 0.591V

reference:

When not used in a design OFS+, OFS-, and MARCTRL

should be left floating. To prevent damage to the part, OFS+

and OFS- should not be tied to VCC or PVCC.

Reference Output Buffer

The internal buffer’s output tracks the unmargined system

reference. It has a 19mA drive capability, with maximum and

minimum output voltage capabilities of VCC and GND

respectively. Its capacitive loading can range from 1µF to

above 17.6µF, which is designed for 1 to 8 DIMM systems in

DDR (Dual Data Rate) applications. 1µF of capacitance

should always be present on REFOUT. It is not designed to

drive a resistive load and any such load added to the system

should be kept above 300kΩ total impedance. The

Reference Output Buffer should not be left floating.

Reference Input

The REFIN pin allows the user to bypass the internal 0.591V

reference with an external reference. Asynchronously, if

REFIN is NOT within ~1.8V of VCC, the external reference

pin is used as the control reference instead of the internal

0.591V reference. The minimum usable REFIN voltage is

~68mV, while the maximum is VCC - 1.8V - V

MARG

(if

present).

MARG_DOWN

REF

---------------

MARG

OFS-

---------------------

•=

MARG_UP

REF

---------------

MARG

OFS+

---------------------

•=

(EQ. 8

)

pct_DOWN

MARG

OFS-

---------------------

•=

PCT_UP

MARG

OFS+

---------------------

•=

(EQ. 9)

FIGURE 5. SIMPLIFIED REFERENCE BUFFER

OTA

800mV

REF_MARG

ISL6540A

STATE

MACHINE

REFERENCE

REF

= 0.591V

REFIN

REFOUT

VCC

MARGINING

BLOCK

ISL6540A

FN6288.5

October 7, 2008

Internal Reference and System Accuracy

The internal reference is trimmed to 0.591V. The total DC

system accuracy of the system is within ±0.68% over

commercial temperature range, and ±1.00% over industrial

temperature range. System accuracy includes error amplifier

offset, OTA error, and bandgap error. Differential remote

sense offset error is not included. As a result, if the

differential remote sense is used, then an extra 1.9mV of

offset error enters the system. The use of REFIN may add

up to 2.2mV of additional offset error.

Differential Remote Sense Buffer

The differential remote sense buffer is essentially an

instrumentation amplifier with unity gain. The offset is

trimmed to 1.5mV for high system accuracy. As with any

instrumentation amplifier, typically 6µA are sourced from the

VSEN- pin. The output of the remote sense buffer is

connected directly to the internal OV/UV comparator. As a

result, a resistor divider should be placed on the input of the

buffer for proper regulation, as shown in Figure 6. The

VMON pin should be connected to the FB pin by a standard

feed-back network. A small capacitor, C

SEN

in Figure 6, can

be added to filter out noise, typically C

SEN

is chosen so the

corresponding time constant does not reduce the overall

phase margin of the design, typically this is 2x to 10x

switching frequency of the regulator.

As some applications will not use the differential remote

sense, the output of the remote sense buffer can be disabled

(high impedance) by pulling VSEN- within 1.8V of VCC. As

the VMON pin is connected internally to the OV/UV/PGOOD

comparator, an external resistor divider must then be

connected to VMON to provide correct voltage information

for the OV/UV comparator. An RC filter should be used if

VMON is to be connected directly to FB instead of to VOUT

through a separate resistor divider network. This filter

prevents noise injection from disturbing the OV/UV/PGOOD

comparators on VMON. VMON may also be connected to

the SS pin, which completely bypasses the OV/UV/PGOOD

functionality.

Application Guidelines

Layout Considerations

MOSFETs switch very fast and efficiently. The speed with

which the current transitions from one device to another

causes voltage spikes across the interconnecting

impedances and parasitic circuit elements. These voltage

spikes can degrade efficiency, radiate noise into the circuit

and lead to device overvoltage stress. Careful component

layout and printed circuit design minimizes the voltage

spikes in the converter. Consider, as an example, the turnoff

transition of the upper PWM MOSFET. Prior to turnoff, the

upper MOSFET is carrying the output inductor current.

During the turnoff, current stops flowing in the upper

MOSFET and is picked up by the lower MOSFET. Any

inductance in the switched current path generates a large

voltage spike during the switching interval. Careful

component selection, tight layout of the critical components,

and short, wide circuit traces minimize the magnitude of

voltage spikes.

There are two sets of critical components in a DC/DC

converter using a ISL6540A controller. The power

components are the most critical because they switch large

currents and have the potential to create large voltage

spikes, as well as induce noise into sensitive, high

impedance adjacent nodes. Next are small signal

VSEN-

VSEN+

COMP

VMON

OV/UV

ERROR AMP

COMP

SEN

1.8V

VCC

10Ω

VOUT (LOCAL)

GND (LOCAL)

VSENSE+

GAIN=1

VSENSE-

FIGURE 6. SIMPLIFIED UNITY GAIN DIFFERENITAL SENSING IMPLEMENTATION

(REMOTE)

ISL6540A

P1-P3 P4-P6 P7-P9 P10-P12 P13-P15 P16-P18 P19-P21 P22-P22

ISL6540ACRZ

Mfr. #:

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