19
FN6288.5
October 7, 2008
It is recommended that a mathematical model is used to plot
the loop response. Check the loop gain against the error
amplifier’s open-loop gain. Verify phase margin results and
adjust as necessary. The following equations describe the
frequency response of the modulator (G
MOD
), feedback
compensation (G
FB
) and closed-loop response (G
CL
):
As before when tieing VFF to VIN terms in the previous
equations can be simplified as shown in Equation 17:
COMPENSATION BREAK FREQUENCY EQUATIONS
Figure 10 shows an asymptotic plot of the DC/DC converter’s
gain vs frequency. The actual modulator gain has a high gain
peak dependent on the quality factor (Q) of the output filter,
which is not shown. Using the previous guidelines should yield
a compensation gain similar to the curve plotted. The open loop
error amplifier gain bounds the compensation gain. Check the
compensation gain at F
P2
against the capabilities of the error
amplifier. The closed loop gain, G
CL
, is constructed on the
log-log graph of Figure 10 by adding the modulator gain,
G
MOD
(in dB), to the feedback compensation gain, G
FB
(in
dB). This is equivalent to multiplying the modulator transfer
function and the compensation transfer function and then
plotting the resulting gain.
A stable control loop has a gain crossing with close to a
-20dB/decade slope and a phase margin greater than 45°.
Include worst case component variations when determining
phase margin. The mathematical model presented makes a
number of approximations and is generally not accurate at
frequencies approaching or exceeding half the switching
frequency. When designing compensation networks, select
target crossover frequencies in the range of 10% to 30% of
the switching frequency, F
SW
.
Component Selection Guidelines
Output Capacitor Selection
An output capacitor is required to filter the output and supply
the load transient current. The filtering requirements are a
function of the switching frequency and the ripple current.
The load transient requirements are a function of the slew
rate (di/dt) and the magnitude of the transient load current.
These requirements are generally met with a mix of
capacitors and careful layout.
Modern microprocessors produce transient load rates above
1A/ns. High frequency capacitors initially supply the transient
and slow the current load rate seen by the bulk capacitors.
The bulk filter capacitor values are generally determined by
the ESR (effective series resistance) and voltage rating
requirements rather than actual capacitance requirements.
High frequency decoupling capacitors should be placed as
close to the power pins of the load as physically possible. Be
careful not to add inductance in the circuit board wiring that
could cancel the usefulness of these low inductance
components. Consult with the manufacturer of the load on
specific decoupling requirements. For example, Intel
recommends that the high frequency decoupling for the
Pentium Pro be composed of at least forty (40) 1.0µF
ceramic capacitors in the 1206 surface-mount package.
Follow on specifications have only increased the number
and quality of required ceramic decoupling capacitors.
Use only specialized low-ESR capacitors intended for
switching-regulator applications for the bulk capacitors. The
bulk capacitor’s ESR will determine the output ripple voltage
and the initial voltage drop after a high slew-rate transient.
An aluminum electrolytic capacitor's ESR value is related to
the case size with lower ESR available in larger case sizes.
R
3
R
1
F
SW
F
LC
------------
1
----------------------
=
C
3
1
2π R
3
0.7 F
SW
⋅⋅
-------------------------------------------------
=
(EQ. 15)
G
MOD
f()
D
MAX
V
IN
V
OSC
-------------------------------
1sf() ESR C⋅⋅+
1sf() ESR DCR+()C⋅⋅s
2
f() LC⋅⋅++
-----------------------------------------------------------------------------------------------------------
=
G
FB
f()
1sf() R
2
C
1
⋅⋅+
sf() R
1
C
1
C
2
+()⋅⋅
----------------------------------------------------
=
1sf() R
1
R
3
+()C
3
⋅⋅+
1sf() R
3
C
3
⋅⋅+()1sf() R
2
C
1
C
2
C
1
C
2
+
---------------------
⎝⎠
⎜⎟
⎛⎞
⋅⋅+
⎝⎠
⎜⎟
⎛⎞
-------------------------------------------------------------------------------------------------------------------------
G
CL
f() G
MOD
f() G
FB
f()=
where s f(), 2π fj⋅⋅=
(EQ. 16)
D
MAX
V
IN
V
OSC
-------------------------------
1V
IN
0.16 V
IN
-------------------------- -
6.25==
(EQ. 17)
F
Z1
1
2π R
2
C
1
⋅⋅
------------------------------ -
=
F
Z2
1
2π R
1
R
3
+()C
3
⋅⋅
-------------------------------------------------
=
F
P1
1
2π R
2
C
1
C
2
C
1
C
2
+
---------------------
⋅⋅
---------------------------------------------
=
F
P2
1
2π R
3
C
3
⋅⋅
------------------------------ -
=
(EQ. 18)
0
F
P1
F
Z2
OPEN LOOP E/A GAIN
F
Z1
F
P2
F
LC
F
CE
COMPENSATION GAIN
GAIN
FREQUENCY
MODULATOR GAIN
FIGURE 10. ASYMPTOTIC BODE PLOT OF CONVERTER GAIN
CLOSED LOOP GAIN
20
D
MAX
V
IN
V
OSC
-----------------------------------log
20
R2
R1
--------
⎝⎠
⎛⎞
log
LOG
LOG
F
0
G
MOD
G
FB
G
CL
ISL6540A
20
FN6288.5
October 7, 2008
However, the equivalent series inductance (ESL) of these
capacitors increases with case size and can reduce the
usefulness of the capacitor to high slew-rate transient
loading. Unfortunately, ESL is not a specified parameter.
Work with your capacitor supplier and measure the
capacitor’s impedance with frequency to select a suitable
component. In most cases, multiple electrolytic capacitors of
small case size perform better than a single large case
capacitor.
Output Inductor Selection
The output inductor is selected to meet the output voltage
ripple requirements and minimize the converter’s response
time to the load transient. The inductor value determines the
converter’s ripple current and the ripple voltage is a function
of the ripple current. The ripple voltage and current are
approximated by Equation 19:
Increasing the value of inductance reduces the ripple current
and voltage. However, the large inductance values reduce
the converter’s response time to a load transient.
One of the parameters limiting the converter’s response to a
load transient is the time required to change the inductor
current. Given a sufficiently fast control loop design, the
ISL6540A will provide either 0% or 100% duty cycle in
response to a load transient. The response time is the time
required to slew the inductor current from an initial current
value to the transient current level. During this interval the
difference between the inductor current and the transient
current level must be supplied by the output capacitor.
Minimizing the response time can minimize the output
capacitance required.
The response time to a transient is different for the
application of load and the removal of load. Equation 20
gives the approximate response time interval for application
and removal of a transient load:
where: I
TRAN
is the transient load current step, t
RISE
is the
response time to the application of load, and t
FALL
is the
response time to the removal of load. With a lower input
source such as 1.8V or 3.3V, the worst case response time
can be either at the application or removal of load and
dependent upon the output voltage setting. Be sure to check
both of these equations at the minimum and maximum
output levels for the worst case response time.
Input Capacitor Selection
Use a mix of input bypass capacitors to control the voltage
overshoot across the MOSFETs. Use small ceramic
capacitors for high frequency decoupling and bulk capacitors
to supply the current needed each time Q
1
turns on. Place the
small ceramic capacitors physically close to the MOSFETs
and between the drain of Q
1
and the source of Q
2
.
The important parameters for the bulk input capacitor are the
voltage rating and the RMS current rating. For reliable
operation, select the bulk capacitor with voltage and current
ratings above the maximum input voltage and largest RMS
current required by the circuit. The capacitor voltage rating
should be at least 1.25x greater than the maximum input
voltage and a voltage rating of 1.5x is a conservative
guideline. The RMS current rating requirement for the input
capacitor of a buck regulator is approximated in Equation 21.
For a through-hole design, several electrolytic capacitors
(Panasonic HFQ series or Nichicon PL series or Sanyo
MV-GX or equivalent) may be needed. For surface mount
designs, solid tantalum capacitors can be used, but caution
must be exercised with regard to the capacitor surge current
rating. These capacitors must be capable of handling the
surge-current at power-up. Figure 11 provides an easy
graphical approximation of the input RMS requirements for a
single-phase buck converter.
MOSFET Selection/Considerations
The ISL6540A requires 2 N-Channel power MOSFETs.
These should be selected based upon r
DS(ON)
, gate supply
requirements, and thermal management requirements.
In high-current applications, the MOSFET power dissipation,
package selection and heatsink are the dominant design
factors. The power dissipation includes two loss
ΔI =
V
IN
- V
OUT
F
S
x L
--------------------------------
V
OUT
V
IN
----------------
ΔV
OUT
= ΔIESR×
(EQ. 19)
t
FALL
L
O
I
TRAN
×
V
OUT
-------------------------------
=t
RISE
L
O
I
TRAN
×
V
IN
V
OUT
------------------------------- -
=
(EQ. 20)
I
IN RMS,
I
O
2
DD
2
()
IΔ
2
12
--------
D+=
D
V
O
VIN
----------
=
OR
I
INRMS
K
ICM
I
O
=
(EQ. 21)
FIGURE 11. INPUT-CAPACITOR CURRENT MULTIPLIER FOR
SINGLE-PHASE BUCK CONVERTER
0.0
0.1
0.2
0.3
0.4
0.5
0.6
0 0.1 0.2 0.3 0.4 0.5 0.6 0.7 0.8 0.9 1.0
K
ICM
DUTY CYCLE (D)
ΔI
LOUT
= 0.25 x I
out
ΔI
LOUT
= 0.5 x I
out
ΔI
LOUT
= 0
0.0
0.2
0.3
ISL6540A
21
All Intersil U.S. products are manufactured, assembled and tested utilizing ISO9000 quality systems.
Intersil Corporation’s quality certifications can be viewed at www.intersil.com/design/quality
Intersil products are sold by description only. Intersil Corporation reserves the right to make changes in circuit design, software and/or specifications at any time without
notice. Accordingly, the reader is cautioned to verify that data sheets are current before placing orders. Information furnished by Intersil is believed to be accurate and
reliable. However, no responsibility is assumed by Intersil or its subsidiaries for its use; nor for any infringements of patents or other rights of third parties which may result
from its use. No license is granted by implication or otherwise under any patent or patent rights of Intersil or its subsidiaries.
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FN6288.5
October 7, 2008
components; conduction loss and switching loss. The
conduction losses are the largest component of power
dissipation for both the upper and the lower MOSFETs.
These losses are distributed between the two MOSFETs
according to duty factor (see the equations below). The
upper MOSFET exhibits turn-on and turn-off switching
losses as well as the reverse recover loss, while the
synchronous rectifier exhibits body-diode conduction losses
during the leading and trailing edge dead times.
where D is the duty cycle = V
O
/VIN; Q
rr
is the reverse
recover charge; t
DL
and t
DT
are leading and trailing edge
dead time, and t
ON
and t
OFF
are the switching intervals.
These equations do not include the gate-charge losses that
are proportional to the total gate charge and the switching
frequency and partially dissipated by the internal gate
resistance of the MOSFETs. Ensure that both MOSFETs are
within their maximum junction temperature at high ambient
temperature by calculating the temperature rise according to
package thermal-resistance specifications. A separate
heatsink may be necessary depending upon MOSFET
power, package type, ambient temperature and air flow.
P
LOWER
I
O
2
IΔ
2
12
--------
+
⎝⎠
⎛⎞
r
DS ON(),L
N
L
---------------------------
1D()P
DEAD
+=
P
DEAD
I
O
IΔ
12
------
+
⎝⎠
⎛⎞
V
DT
t
DT
I
O
IΔ
12
------
⎝⎠
⎛⎞
V
DL
t
DL
+ F
S
=
P
SW
I
O
IΔ
12
------
+
⎝⎠
⎛⎞
t
OFF
I
O
IΔ
12
------
⎝⎠
⎛⎞
t
ON
+ VIN F
S
=
P
UPPER
I
O
2
IΔ
2
12
--------
+
⎝⎠
⎛⎞
r
DS ON(),U
N
U
----------------------------
DP
SW
P
Qrr
++=
P
Qrr
Q
rr
VIN F
S
=
(EQ. 22)
ISL6540A

ISL6540ACRZ

Mfr. #:
Manufacturer:
Renesas / Intersil
Description:
Switching Controllers PB FREE 3 3V-20V INPUT SYNC PWM CONT
Lifecycle:
New from this manufacturer.
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