9
FN6288.5
October 7, 2008
Functional Pin Description
VSEN+ (Pin 1)
This pin provides differential remote sense for the ISL6540A.
It is the positive input of a standard instrumentation amplifier
topology with unity gain, and should connect to the positive
rail of the load/processor. The voltage at this pin should be
set equal to the internal system reference voltage (0.591V
typical).
VSEN- (Pin 2)
This pin provides differential remote sense for the regulator.
It is the negative input of the instrumentation amplifier, and
should connect to the negative rail of the load/processor.
Typically 6µA is sourced from this pin. The output of the
remote sense buffer is disabled (High Impedance) by pulling
VSEN- to VCC.
REFOUT (Pin 3)
This pin connects to the unmargined system reference
through an internal buffer. It has a 19mA drive capability with
an output common mode range of GND to VCC. The
REFOUT buffer requires at least 1µF of capacitive loading to
be stable. This pin should not be left floating.
REFIN (Pin 4)
When the external reference pin (REFIN) is NOT within
~1.8V of VCC, the REFIN pin is used as the system
reference instead of the internal 0.591V reference. The
recommended REFIN input voltage range is ~68mV to
VCC - 1.8V.
SS (Pin 5)
This pin provides soft-start functionality for the ISL6540A. A
capacitor connected to ground along with the internal 37µA
Operational Transconductance Amplifier (OTA), sets the
soft-start interval of the converter. This pin is directly
connected to the non-inverting input of the error amplifier. To
prevent noise injection into the error amplifier the SS
capacitor should be located next to the SS and GND pins.
OFS+ (Pin 6)
This pin sets the positive margining offset voltage. Resistors
should be connected to GND (R
OFS+
) and OFS- (R
MARG
)
from this pin. With MAR_CTRL logic low, the internal 0.591V
reference is developed at the OFS+ pin across resistor
R
OFS+
. The voltage on OFS+ is driven from OFS- through
R
MARG
. The resulting voltage differential between OFS+
and OFS- is divided by 5 and imposed on the system
reference. The maximum designed offset of 1V between
OFS+ and OFS- pins translates to a 200mV offset.
OFS- (Pin 7)
This pin sets the negative margining offset voltage. Resistors
should be connected to GND (R
OFS-
) and OFS+ (R
MARG
)
from this pin. With MAR_CTRL logic low, the internal 0.591V
reference is developed at the OFS- pin across resistor
R
OFS-
. The voltage on OFS- is driven from OFS+ through
R
MARG
. The resulting voltage differential between OFS+
and OFS- is divided by 5 and imposed on the system
reference. The maximum designed offset of -1V between
OFS+ and OFS- pins translates to a -200mV offset of the
system reference.
VCC (Pin 8, Analog Circuit Bias)
This pin provides power for the ISL6540A analog circuitry.
The pin should be connected to a 2.9V to 5.5V bias through
an RC filter from PVCC to prevent noise injection into the
analog circuitry. A 0.1µF capacitor is sufficient for decoupling
of the VCC pin. The time constant of the RC filter should be
no more than 10µs. This pin can be powered off the internal
or external linear regulator options.
MARCTRL (Pin 9)
The MARCTRL pin controls margining function, a logic high
enables positive margining, a logic low sets negative
margining, a high impedance disables margining.
PG_DLY (Pin 10)
Provides the ability to delay the output of the PGOOD
assertion by connecting a capacitor from this pin to GND. A
0.1µF capacitor produces approximately a 7ms delay.
PGOOD (Pin 11)
Provides an open drain Power-Good signal when the output
is within 9% of nominal output regulation point with 6%
hysteresis (15%/9%), and after soft-start is complete.
PGOOD monitors the VMON pin.
EN (Pin 12)
This pin is compared with an internal 0.50V reference and
enables the soft-start cycle. This pin also can be used for
voltage monitoring. A 10µA current source to GND is active
while the part is disabled, and is inactive when the part is
enabled. This provides functionality for programmable
hysteresis when the EN pin is used for voltage monitoring. In
many applications, this pin is susceptible to excessive
V
PG_DLY
PGOOD Delay Threshold Voltage 1.45 1.49 1.52 V
I
PG_LOW
PGOOD Low Output Voltage I
PGOOD
= 5mA - - 0.150 V
I
PG_MAX
Maximum Sinking Current V
PGOOD
= 0.8V 23 - - mA
V
PG_MAX
Maximum Open Drain Voltage VCC = 3.3V - 6 - V
Electrical Specifications Recommended Operating Conditions, Unless Otherwise Noted. Parts are 100% tested at +25°C. Temperature
limits established by characterization and are not production tested. (Continued)
SYMBOL PARAMETER TEST CONDITIONS MIN TYP MAX UNITS
ISL6540A
