5
LT1168
1168fa
Note 1: Stresses beyond those listed under Absolute Maximum Ratings
may cause permanent damage to the device. Exposure to any Absolute
Maximum Rating condition for extended periods may affect device
reliability and lifetime.
Note 2: If the input voltage exceeds the supplies, the input current should
be limited to less than 20mA.
Note 3: A heat sink may be required to keep the junction temperature
below absolute maximum.
Note 4: The LT1168AC/LT1168C are guaranteed functional over the
operating temperature range of –40°C and 85°C.
Note 5: The LT1168AC/LT1168C are guaranteed to meet specified
performance from 0°C to 70°C. The LT1168AC/LT1168C are designed,
characterized and expected to meet specified performance from –40°C
to 85°C but are not tested or QA sampled at these temperatures. The
LT1168AI/LT1168I are guaranteed to meet specified performance from
–40°C to 85°C.
Note 6: Typical parameters are defined as the 60% of the yield parameter
distribution.
Note 7: Does not include the tolerance of the external gain resistor R
G
.
Note 8: This parameter is measured in a high speed automatic tester that
does not measure the thermal effects with longer time constants. The
magnitude of these thermal effects are dependent on the package used,
heat sinking and air flow conditions.
Note 9: This parameter is not 100% tested.
Note 10: Hysteresis in offset voltage is created by package stress that
differs depending on whether the IC was previously at a higher or lower
temperature. Offset voltage hysteresis is always measured at 25°C, but
the IC is cycled to 85°C I-grade (or 70°C C-grade) or –40°C I-grade
(0°C C-grade) before successive measurement. 60% of the parts will
pass the typical limit on the data sheet.
The ● denotes the specifications which apply over the –40°C ≤ T
A
≤ 85°C
temperature range. V
S
= ±15V, V
CM
= 0V, R
L
= 10k unless otherwise noted. (Note 5)
ELECTRICAL CHARACTERISTICS
LT1168AI LT1168I
SYMBOL PARAMETER CONDITIONS (Note 6) MIN TYP MAX MIN TYP MAX UNITS
V
OST
Total Input Referred Offset Voltage V
OST
= V
OSI
+ V
OSO
/G
V
OSI
Input Offset Voltage ● 20 75 25 100 µV
V
OSIH
Input Offset Voltage Hysteresis (Notes 7, 10) ● 3.0 3.0 µV
V
OSO
Output Offset Voltage ● 180 500 200 600 µV
V
OSOH
Output Offset Voltage Hysteresis (Notes 7, 10) ● 30 30 µV
V
OSI
/T Input Offset Drift (RTI) (Note 9) ● 0.05 0.3 0.06 0.4 µV/°C
V
OSO
/T Output Offset Drift (Note 9) ● 0.8 5 1 6 µV/°C
I
OS
Input Offset Current ● 110 550 120 700 pA
I
OS
/T Input Offset Current Drift ● 0.3 0.3 pA/°C
I
B
Input Bias Current ● 120 500 220 800 pA
I
B
/T Input Bias Current Drift ● 1.4 1.4 pA/°C
V
CM
Input Voltage Range V
S
= ±2.3V to ±5V ● –V
S
+ 2.1 +V
S
– 1.3 –V
S
+ 2.1 +V
S
– 1.3 V
V
S
= ±5V to ±18V ● –V
S
+ 2.1 +V
S
– 1.4 –V
S
+ 2.1 +V
S
– 1.4 V
CMRR Common Mode 1k Source Imbalance,
Rejection Ratio V
CM
= 0V to ±10V
G = 1
● 86 90 81 90 dB
G = 10
● 98 105 95 105 dB
G = 100
● 114 118 112 118 dB
G = 1000
● 116 133 112 133 dB
PSRR Power Supply V
S
= ±2.3V to ±18V
Rejection Ratio G = 1
● 100 112 95 112 dB
G = 10
● 120 125 115 125 dB
G = 100
● 125 132 120 132 dB
G = 1000
● 128 140 125 140 dB
I
S
Supply Current ● 420 650 420 650 µA
V
OUT
Output Voltage Swing V
S
= ±2.3V to ±5V ● –V
S
+ 1.4 +V
S
– 1.3 –V
S
+ 1.4 +V
S
– 1.3 V
V
S
= ±5V to ±18V ● –V
S
+ 1.6 +V
S
– 1.5 –V
S
+ 1.6 +V
S
– 1.5 V
I
OUT
Output Current ● 15 22 15 22 mA
SR Slew Rate ● 0.22 0.41 0.22 0.42 V/µs
V
REF
Voltage Range (Note 9) ● –V
S
+ 1.6 +V
S
– 1.6 –V
S
+ 1.6 +V
S
– 1.6 V
