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MAX1011CEG+

P1-P3P4-P6P7-P9P10-P12
General Description
The MAX1011 is a 6-bit analog-to-digital converter
(ADC) that combines high-speed, low-power operation
with a user-selectable input range, an internal refer-
ence, and a clock oscillator. The ADC converts analog
signals into binary-coded digital outputs at sampling
rates up to 90Msps. The ability to directly interface with
baseband signals makes the MAX1011 ideal for use in
a wide range of communications and instrumentation
applications.
The MAX1011’s input amplifier features a true differential
input, a -0.5dB analog bandwidth of 55MHz, and a user-
programmable input full-scale range of 125mVp-p,
250mVp-p, or 500mVp-p. With an AC-coupled signal,
input offset is typically less than 1/4LSB. Dynamic per-
formance is 5.85 effective number of bits (ENOB) with a
20MHz analog input signal, or 5.7 ENOB with a 50MHz
signal.
The MAX1011 operates with +5V analog and +3.3V digi-
tal supplies for easy interfacing to +3.3V-logic-compatible
digital signal processors and microprocessors. It comes
in a 24-pin QSOP package.
Applications
IF Sampling Receivers
VSAT Receivers
Wide Local Area Networks (WLANs)
Instrumentation
Features
♦ High Sampling Rate: 90Msps
♦ Low Power Dissipation: 215mW
♦ Excellent Dynamic Performance:
5.85 ENOB with 20MHz Analog Input
5.7 ENOB with 50MHz Analog Input
♦ ±1/4LSB INL and DNL (typ)
♦ ±1/4LSB Input Offset (typ)
♦ Internal Bandgap Voltage Reference
♦ Internal Oscillator with Overdrive Capability
♦ 55MHz (-0.5dB) Bandwidth Input Amplifier with
True Differential Input
♦ User-Selectable Full-Scale Range
(125mVp-p, 250mVp-p, or 500mVp-p)
♦ Single-Ended or Differential Input Drive
♦ Flexible, 3.3V, CMOS-Compatible Digital Outputs
MAX1011
Low-Power, 90Msps, 6-Bit ADC
________________________________________________________________
Maxim Integrated Products
1
MAX1011
D0–D5
DCLK
TNK+
TNK-
INPUT
AMP
IN+
IN-
GAIN
DATA
BUFFER
6
ADC
VREF
BANDGAP
REFERENCE
OCC+ OCC-
6
OFFSET
CORREC-
TION
CLOCK
OUT
CLOCK
DRIVER
Functional Diagram
19-1335; Rev 0a; 2/98
PART
MAX1011CEG 0°C to +70°C
TEMP. RANGE PIN-PACKAGE
24 QSOP
EVALUATION KIT
AVAILABLE
Pin Configuration appears at end of data sheet.
For free samples & the latest literature: http://www.maxim-ic.com, or phone 1-800-998-8800
For small orders, phone 408-737-7600 ext. 3468.
Ordering Information
MAX1011
Low-Power, 90Msps, 6-Bit ADC
2 _______________________________________________________________________________________
ABSOLUTE MAXIMUM RATINGS
DC ELECTRICAL CHARACTERISTICS
(V
CC
= +5V ±5%, V
CCO
= 3.3V ±300mV, T
A
= T
MIN
to T
MAX
, unless otherwise noted.)
Stresses beyond those listed under “Absolute Maximum Ratings” may cause permanent damage to the device. These are stress ratings only, and functional
operation of the device at these or any other conditions beyond those indicated in the operational sections of the specifications is not implied. Exposure to
absolute maximum rating conditions for extended periods may affect device reliability.
V
CC
to GND ..........................................................-0.3V to +6.5V
V
CCO
to OGND......................................................-0.3V to +6.5V
GND to OGND ......................................................-0.3V to +0.3V
Digital and Clock Output Pins to OGND...-0.3V to V
CCO
(10sec)
All Other Pins to GND...............................................-0.3V to V
CC
Continuous Power Dissipation (T
A
= +70°C)
24-Pin QSOP (derate 10mW/°C above +70°C)...........800mW
Operating Temperature Range...............................0°C to +70°C
Storage Temperature Range.............................-65°C to +150°C
Lead Temperature (soldering, <10sec)...........................+300°C
CONDITIONS
LSB-0.5 ±0.25 0.5INLIntegral Nonlinearity
Bits6RESResolution
UNITSMIN TYP MAXSYMBOLPARAMETER
GAIN = open (mid gain)
GAIN = V
CC
(high gain)
No missing codes over temperature
237.5 250 262.5V
FSM
118.75 125 131.25V
FSH
LSB-0.5 ±0.25 0.5DNLDifferential Nonlinearity
Other analog input driven with external source
(Note 2)
Guaranteed by design
V1.75 2.75V
CM
GAIN = GND (low gain)
Common-Mode Voltage Range
pF1.5 3C
IN
Input Capacitance
kΩ13 20 29R
IN
Input Resistance
V2.25 2.35 2.45V
AOC
Input Open-Circuit Voltage
mVp-p
475 500 525V
FSL
Full-Scale Input Range
Other oscillator input tied to V
CC
+ 0.3V
I
SOURCE
= 50µA V0.7V
CCO
V
OH
Digital Outputs Logic-High
Voltage
kΩ4.8 8 12.1R
OSC
Oscillator Input Resistance
I
SINK
= 400µA V0.5V
OL
Digital Outputs Logic-Low
Voltage
V
CC
= 4.75V to 5.25V (Note 3)
20MHz, full-scale analog inputs,
C
L
= 15pF (Note 4)
mW215PDPower Dissipation
mA8.5 13.8I
CCO
Digital Outputs Supply Current
dB-65 -40PSRRPower-Supply Rejection Ratio
mA37 63.5I
CC
Supply Current
DC ACCURACY (Note 1)
INVERTING AND NONINVERTING ANALOG INPUTS
OSCILLATOR INPUTS
DIGITAL OUTPUTS (D0–D5)
POWER SUPPLY
MAX1011
Low-Power, 90Msps, 6-Bit ADC
_______________________________________________________________________________________ 3
AC ELECTRICAL CHARACTERISTICS
(V
CC
= +5V ±5%, V
CCO
= 3.3V ±300mV, T
A
= +25°C, unless otherwise noted.)
Note 1: Best-fit straight-line linearity method.
Note 2: A typical application will AC couple the analog input to the DC bias level present at the analog inputs (typically 2.35V).
However, it is also possible to DC couple the analog input (using differential or single-ended drive) within this common-
mode input range (Figures 4 and 5).
Note 3: PSRR is defined as the change in the mid-gain, full-scale range as a function of the variation in V
CC
supply voltage,
expressed in decibels.
Note 4: The current in the V
CCO
supply is a strong function of the capacitive loading on the digital outputs. To minimize supply tran-
sients and achieve optimal dynamic performance, reduce the capacitive-loading effects by keeping line lengths on the dig-
ital outputs to a minimum.
Note 5: Offset-correction compensation enabled, 0.22µF at compensation inputs (Figures 2 and 3).
Note 6: t
PD
and t
SKEW
are measured from the 1.4V level of the output clock, to the 1.4V level of either the rising or falling edge of a
data bit. t
DCLK
is measured from the 50% level of the clock-overdrive signal on TNK+ to the 1.4V level of DCLK. The capac-
itive load on the outputs is 15pF.
GAIN = GND, open, V
CC
GAIN = open (mid gain), f
IN
= 50MHz,
-1dB below full scale
GAIN = open (mid gain)
5.7
ENOB
M
5.6 5.85
Effective Number of Bits
GAIN = open (mid gain)
GAIN = GND (low gain)
Guaranteed by design
CONDITIONS
MHz55BWAnalog Input -0.5dB Bandwidth
Msps90f
MAX
Maximum Sample Rate
GAIN = V
CC
(high gain)
LSBOFFInput Offset (Note 5) -0.5 0.5
dB35.5 37SINAD
Signal-to-Noise Plus Distortion
Ratio
Bits
5.85ENOB
L
5.8ENOB
H
(Note 6)
(Note 6)
ns1t
SKEW
Data Valid Skew
ns3.0t
PD
Clock to Data Propagation
Delay
UNITSMIN TYP MAXSYMBOLPARAMETER
TNK+ to DCLK (Note 6) ns4.5t
DCLK
Input to DCLK Delay
Figure 8 ns5.5t
AD
Aperture Delay
Figure 8
clock
cycle
1PDPipeline Delay
TIMING CHARACTERISTICS (Data outputs: R
L
= 1MΩ, C
L
= 15pF)
DYNAMIC PERFORMANCE (Gain = open, external 90MHz clock (Figure 7), V
IN
= 20MHz sine, amplitude -1dB below
full scale, unless otherwise noted.)
P1-P3P4-P6P7-P9P10-P12

MAX1011CEG+

Mfr. #:
Buy MAX1011CEG+
Manufacturer:
Maxim Integrated
Description:
Analog to Digital Converters - ADC Low-Power 90Msps 6-Bit
Lifecycle:
New from this manufacturer.
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