MAX1011CEG+ Datasheet MAX1011CEG+ | P7-P9

For applications where a DC component of the input

signal is present, Figures 4 and 5 show single-ended

and differential DC-coupled input circuits. The amplifi-

er’s input common-mode voltage range extends from

1.75V to 2.75V. To prevent attenuation of the input

signal’s DC component in this mode, disable the offset-

correction amplifier by grounding the OCC+ and OCC-

pins (Figures 4 and 5).

ADC

The ADC block receives the analog signal from the

input amplifier. The ADC uses flash conversion with 63

fully differential comparators to digitize the analog input

signal into a 6-bit output in offset binary format.

The MAX1011 features a proprietary encoding scheme

that ensures no more than 1LSB dynamic encoding

error. Dynamic encoding errors resulting from meta-

stable states may occur when the analog input voltage,

at the time the sample is taken, falls close to the deci-

sion point for any one of the input comparators. The

resulting output code for typical converters can be

incorrect, including false full- or zero-scale outputs. The

MAX1011’s unique design reduces the magnitude of

this type of error to 1LSB.

Internal Voltage Reference

An internal buffered-bandgap reference is included on

the MAX1011 to drive the ADC’s reference ladder. The

on-chip reference and buffer eliminate any external

(high-impedance) connections to the reference ladder,

minimizing the potential for noise coupling from exter-

nal circuitry while ensuring that the voltage reference,

input amplifier, and reference ladder track well with

variations of temperature and power supplies.

Oscillator Circuit

The MAX1011 includes a differential oscillator, which is

controlled by an external parallel resonant (tank) net-

work as shown in Figure 6. Alternatively, the oscillator

may be overdriven with an external clock source as

shown in Figure 7.

Internal Clock Operation (Tank)

If the tank circuit is used, the resonant inductor should

have a sufficiently high Q and a self-resonant frequen-

cy (SRF) of at least twice the intended oscillator fre-

quency. Coilcraft’s 1008HS-221, with an SRF of

700MHz and a Q of 45, works well for this application.

Generate different clock frequency ranges by adjusting

varactor and tank elements.

An internal clock-driver buffer is included to provide

sharp clock edges to the internal flash comparators.

The buffer ensures that the comparators are simultane-

ously clocked, maximizing the ADC’s effective number

of bits (ENOB) performance.

MAX1011

Low-Power, 90Msps, 6-Bit ADC

_______________________________________________________________________________________ 7

Figure 4. Single-Ended DC-Coupled Input

Figure 5. Differential DC-Coupled Input

MAX1011

INPUT

AMP

20k

2.35V INTERNAL REFERENCE

20k

IN+

OCC+ OCC-

IN-

OFFSET CORRECTION DISABLED

SOURCE

1.75V TO 2.75V

OFFSET

CORREC-

TION

MAX1011

INPUT

AMP

20k

2.35V INTERNAL REFERENCE

20k

IN+

OCC+ OCC-

IN-

OFFSET CORRECTION DISABLED

SOURCE

DIFFERENTIAL SOURCE

WITH COMMON MODE

FROM 1.75V TO 2.75V.

OFFSET

CORREC-

TION

MAX1011

External Clock Operation

To accommodate designs that use an external clock,

the MAX1011’s internal oscillator can be overdriven by

an external clock source (Figure 7). The external clock

source should be a sinusoid to minimize clock phase

noise and jitter, which can degrade the ADC’s ENOB

performance. AC couple the clock source (recom-

mended voltage level is approximately 1Vp-p) to the

oscillator inputs (Figure 7).

Output Data Format

The conversion results are output on a 6-bit-wide data

bus. Data is latched into the ADC output latch following

a pipeline delay of one clock cycle (Figure 8). Output

data is clocked out of the ADC’s data output pins (D0

through D5) on the rising edge of the clock output

(DCLK), with a DCLK-to-data propagation delay (t

) of

3.0ns. The MAX1011 outputs are +3.3V CMOS-logic

compatible.

Transfer Function

Figure 9 shows the MAX1011’s nominal transfer function.

Output coding is offset binary with 1LSB = FSR / 63.

___________Applications Information

The MAX1011 is designed with separate analog and

digital power-supply and ground connections to isolate

high-current digital noise spikes from the more sensi-

tive analog circuitry. The high-current digital output

ground (OGND) and analog ground (GND) should be

at the same DC level, connected at only one location

on the board. This will provide best noise immunity and

improved conversion accuracy. Use of separate

ground planes is strongly recommended.

The entire board needs good DC bypassing for both

analog and digital supplies. Place the power-supply

bypass capacitors close to where the power is routed

onto the board, i.e., close to the connector. 10µF elec-

trolytic capacitors with low-ESR ratings are recom-

mended. For best effective bits performance, minimize

capacitive loading at the digital outputs. Keep the digi-

tal output traces as short as possible.

The MAX1011 requires a +5V ±5% power supply for

the analog supply (V

) and a +3.3V ±300mV power

supply connected to V

CCO

for the logic outputs.

Bypass each of the V

supply pins to its respective

GND with high-quality ceramic capacitors located as

close to the package as possible (Table 2). Consult the

evaluation kit manual for a suggested layout and

bypassing scheme.

Low-Power, 90Msps, 6-Bit ADC

8 _______________________________________________________________________________________

Figure 7. External Clock Drive Circuit

MAX1011

CLK

DRIVER

TNK-

CLK

= 300mV

p-p

TO 1.25V

p-p

TNK+

50Ω

= 50Ω

50Ω

0.1µF

0.01µFOscillator/Clock

47pFDigital Output

BYPASS

TO GND/

OGND

(PIN)

0.01µFConverter 14

CCO

(PIN)

SUPPLY

FUNCTION

0.01µFAnalog Inputs

CAPACITOR

VALUE

Table 2. Bypassing Guide

Figure 6. Tank Resonator Oscillator

MAX1011

CLK

DRIVER

VARACTOR DIODE PAIR IS M/A-COM MA4ST079CK-287

(SOT23 PACKAGE)

INDUCTOR COILCRAFT 1008HS-221.

TUNE

= 0V TO 8V

OSC

= 70MHz TO 109MHz

TNK-

TNK+

TUNE

220nH

5pF

47pF

47k

10k

______________Dynamic Performance

Signal-to-noise and distortion (SINAD) is the ratio of the

fundamental input frequency’s RMS amplitude to all

other ADC output signals. The output spectrum is limit-

ed to frequencies above DC and below one-half the

ADC sample rate.

The theoretical minimum analog-to-digital noise is

caused by quantization error, and results directly from

the ADC’s resolution: SNR = (6.02N + 1.76)dB, where

N is the number of bits of resolution. Therefore, a per-

fect 6-bit ADC can do no better than 38dB.

The FFT Plot (see

Typical Operating Characteristics

)

shows the result of sampling a pure 20MHz sinusoid at

a 90MHz clock rate. This FFT plot of the output shows

the output level in various spectral bands. The plot has

been averaged to reduce the quantization noise floor

and reveal the low-amplitude spurs. This emphasizes the

excellent spurious-free dynamic range of the MAX1011.

The effective resolution (or effective number of bits) the

ADC provides can be measured by transposing the

equation that converts resolution to SINAD:N= (SINAD

-1.76)/ 6.02 (see

Typical Operating Characteristics

MAX1011

Low-Power, 90Msps, 6-Bit ADC

_______________________________________________________________________________________ 9

Figure 9. Ideal Transfer Function

111111

OUTPUT CODE

111110

111101

100001

100000

011111

011110

000011

000010

000001

000000

-FSR

1LSB

INPUT VOLTAGE (IN+ TO IN-)

FSR

Figure 8. MAX1011 Timing Diagram

DATA OUT

1.4V

DATA VALID N - 1 DATA VALID N

1.4V

50%

SKEW

DCLK

TNK+

(INPUT CLOCK)

DCLK

ANALOG

INPUT

N + 1

N + 2

P1-P3 P4-P6 P7-P9 P10-P12

MAX1011CEG+

Mfr. #:

Buy MAX1011CEG+

Manufacturer:

Maxim Integrated

Description:

Analog to Digital Converters - ADC Low-Power 90Msps 6-Bit

Lifecycle:

New from this manufacturer.

Delivery:

DHL FedEx Ups TNT EMS

Payment:

T/T Paypal Visa MoneyGram Western Union

Products related to this Datasheet

MAX1011CEG+