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LTC1276ACN#PBF

P1-P3P4-P6P7-P9P10-P12P13-P15P16-P18P19-P21P22-P24
13
LTC1273
LTC1275/LTC1276
127356fa
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reference pin. The V
REF
pin must be driven to at least
2.45V to prevent conflict with the internal reference. The
reference should be driven to no more than 4.8V to keep
the input span within the ±5V supplies. In the LTC1273/
LT1276, the input spans are 0V to 5V and ±5V respec-
tively with the internal reference. Driving the reference is
not recommended on the LTC1273/LTC1276 since the
input spans will exceed the supplies and codes will be lost
at full scale.
Figure 7 shows a typical reference, the LT1019A-2.5
connected to the LTC1275. This will provide an improved
drift (equal to the maximum 5ppm/°C of the LT1019A-2.5)
and a ±2.582V full scale.
Figure 8. LTC1273 Unipolar Transfer Characteristic
INPUT VOLTAGE (V)
0V
OUTPUT CODE
FS – 1LSB
LTC1273/75/76 • F08
111...111
111...110
111...101
111...100
000...000
000...001
000...010
000...011
1
LSB
1LSB =
FS
4096
=
5V
4096
UNIPOLAR
ZERO
Figure 9. LTC1275/LTC1276 Bipolar Transfer Characteristic
LTC1273
LTC1275
LTC1276
A
IN
AGND
LTC1273/75/76 • F10a
R4
100Ω
FULL SCALE
ADJUST
R3
10k
R2
10k
R1
50Ω
V
1
–
+
A1
ADDITIONAL PINS OMITTED FOR CLARITY
±20LSB TRIM RANGE
Figure 10a. Full Scale Adjust Circuit
Figure 7. Supplying a 2.5V Reference Voltage
to the LTC1275 with the LT1019A-2.5
3Ω
INPUT RANGE
±2.58V
LTC1275
A
IN
AGND
V
REF
10µF
LTC1273/75/76 • F07
LT1019A-2.5
V
IN
GND
V
OUT
5V
UNIPOLAR/BIPOLAR OPERATION AND ADJUSTMENT
Figure 8 shows the ideal input/output characteristics for
the LTC1273. The code transitions occur midway between
successive integer LSB values (i.e., 1/2LSB, 1 1/2LSBs,
2 1/2LSBs, ... FS – 1 1/2LSBs). The output code is natural
binary with 1LSB = FS/4096 = 5V/4096 = 1.22mV. Figure
9 shows the input/output transfer characteristics for the
LTC1275/LTC1276 in 2’s complement format. As stated in
the figure, 1LSB for LTC1275/LTC1276 are 1.22mV and
2.44mV respectively.
Unipolar Offset and Full Scale Adjustment (LTC1273)
In applications where absolute accuracy is important,
offset and full scale errors can be adjusted to zero. Figure
10a shows the extra components required for full scale
error adjustment. If both offset and full scale adjustments
are needed, the circuit in Figure 10b can be used. Offset
INPUT VOLTAGE (V)
0V
OUTPUT CODE
–1
LSB
LTC1273/75/76 • F09
011...111
011...110
000...001
000...000
100...000
100...001
111...110
1
LSB
BIPOLAR
ZERO
111...111
111...110
FS/2 – 1LSB–FS/2
FS = 5V (LTC1275)
FS = 10V (LTC1276)
1LSB = FS/4096
14
LTC1273
LTC1275/LTC1276
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A
IN
LTC1273/75/76 • F10c
R2
10k
R4
100k
R1
10k
ANALOG
INPUT
±2.5V (LTC1275)
±5V (LTC1276)
R3
100k
5V
R8
20k
OFFSET
ADJUST
R6
200Ω
R5
4.3k
FULL SCALE
ADJUST
R7
100k
–
+
LTC1275
LTC1276
–5V
A
IN
LTC1273/75/76 • F10b
R2
10k
R4
100k
R1
10k
10k
5V
R9
20Ω
ANALOG
INPUT
0V TO 5V
R3
100k
5V
R8
10k
OFFSET
ADJUST
R6
400Ω
R5
4.3k
FULL SCALE
ADJUST
R7
100k
–
+
LTC1273
Figure 10b. LTC1273 Offset and Full Scale Adjust Circuit
should be adjusted before full scale. To adjust offset, apply
0.61mV (i.e., 1/2LSB) at the input and adjust the offset
trim until the LTC1273 output code flickers between 0000
0000 0000 and 0000 0000 0001. To adjust full scale, apply
an analog input of 4.99817V (i.e., FS – 1 1/2LSBs or last
code transition) at the input and adjust the full scale trim
until the LTC1273 output code flickers between 1111 1111
1110 and 1111 1111 1111. It should be noted that if
negative ADC offsets need to be adjusted or if an output
swing to ground is required, the op amp in Figure 10b
requires a negative power supply.
Bipolar Offset and Full Scale Adjustment
(LTC1275/LTC1276)
Bipolar offset and full scale errors are adjusted in a similar
fashion to the unipolar case. Figure 10a shows the extra
components required for full scale error adjustment. If
both offset and full scale adjustments are needed, the
circuit in Figure 10c can be used. Again, bipolar offset
must be adjusted before full scale error. Bipolar offset
adjustment is achieved by trimming the offset adjustment
of Figure 10c while the input voltage is 1/2LSB below
ground. This is done by applying an input voltage of
– 0.61mV or – 1.22mV (– 0.5LSB for LTC1275 or LTC1276)
to the input in Figure 10c and adjusting R8 until the ADC
output code flickers between 0000 0000 0000 and 1111
1111 1111. For full scale adjustment, an input voltage of
2.49817V or 4.9963
6V (FS – 1 1/2LSBs for LTC1275 or
LTC1276) is applied to the input and R5 is adjusted until
the output code flickers between 0111 1111 1110 and
0111 1111 1111.
BOARD LAYOUT AND BYPASSING
The LTC1273/LTC1275/LTC1276 are easy to use. To ob-
tain the best performance from the devices a printed
circuit board is required. Layout for the printed circuit
board should ensure that digital and analog signal lines are
separated as much as possible. In particular, care should
be taken not to run any digital track alongside an analog
signal track. The analog input should be screened by
AGND.
High quality tantalum and ceramic bypass capacitors
should be used at the V
DD
and V
REF
pins as shown in Figure
11. For the LTC1275/LTC1276 a 0.1µF ceramic provides
adequate bypassing for the V
SS
pin. The capacitors must
be located as close to the pins as possible. The traces
connecting the pins and the bypass capacitors must be
kept short and should be made as wide as possible.
Noise: Input signal leads to A
IN
and signal return leads
from AGND (Pin 3) should be kept as short as possible to
minimize input noise coupling. In applications where this
is not possible, a shielded cable between source and ADC
is recommended. Also, since any potential difference in
grounds between the signal source and ADC appears as an
Figure 10c. LTC1275/LTC1276 Offset and
Full Scale Adjust Circuit
15
LTC1273
LTC1275/LTC1276
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Figure 11. Power Supply Grounding Practice
LTC1273/75/76 • F11
A
IN
AGND V
REF
V
DD
DGND
LTC1273
DIGITAL
SYSTEM
0.1µF
+
–
ANALOG GROUND PLANE
GROUND CONNECTION
TO DIGITAL CIRCUITRY
ANALOG
INPUT
CIRCUITRY
3 2 24 12
1
0.1µF
10µF10µF
error voltage in series with the input signal, attention
should be paid to reducing the ground circuit impedances
as much as possible.
A single point analog ground plane separate from the logic
system ground should be established at Pin 3 (AGND) or
as close as possible to the ADC, as shown in Figure 11. Pin
12 (DGND) and all other analog grounds should be con-
nected to this single analog ground point. No other digital
grounds should be connected to this analog ground point.
Low impedance analog and digital power supply common
returns are essential to low noise operation of the ADC and
the width for these traces should be as wide as possible.
In applications where the ADC data outputs and control
signals are connected to a continuously active micropro-
cessor bus, it is possible to get errors in conversion
results. These errors are due to feedthrough from the
microprocessor to the ADC. The problem can be elimi-
nated by forcing the microprocessor into a WAIT state
during conversion or by using three-state buffers to iso-
late the ADC data bus.
DIGITAL INTERFACE
The ADCs are designed to interface with microprocessors
as a memory mapped device. The CS and RD control
inputs are common to all peripheral memory interfacing.
The HBEN input serves as a data byte select for 8-bit
processors and is normally either connected to the micro-
processor address bus or grounded.
Internal Clock
These ADCs have an internal clock that eliminates the need
for synchronization between an external clock and the CS
and RD signals found in other ADCs. The internal clock is
factory trimmed to achieve a typical conversion time of
2.45µs, and a maximum conversion time over the full
operating temperature range of 2.7µs. No external adjust-
ments are required and, with the guaranteed maximum
acquisition time of 600ns, throughput performance of
300ksps is assured.
Timing and Control
Conversion start and data read operations are controlled
by three digital inputs: HBEN, CS and RD. Figure 12 shows
the logic structure associated with these inputs. The three
signals are internally gated so that a logic “0” is required
CONVERSION
START (RISING
EDGE TRIGGER)
LTC1273/75/76 • F12
BUSY
FLIP
FLOP
CLEAR
QD
19
21
20
ACTIVE HIGH
ACTIVE HIGH
ENABLE THREE-STATE OUTPUTS
D11....D0/8 = DB11....DB0
ENABLE THREE-STATE OUTPUTS
D11....D8 = DB11....DB8
D7....D4 = LOW
D3/11....D0/8 = DB11....DB8
HBEN
CS
RD
LTC1273/75/76
D11....D0/8 ARE THE ADC DATA OUTPUT PINS
DB11....DB0 ARE THE 12-BIT CONVERSION RESULTS
*
Figure 12. Internal Logic for Control Inputs CS, RD and HBEN
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LTC1276ACN#PBF

Mfr. #:
Buy LTC1276ACN#PBF
Manufacturer:
Analog Devices Inc.
Description:
Analog to Digital Converters - ADC 12-B, 300ksps Smpl A/D Convs w/ Ref
Lifecycle:
New from this manufacturer.
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