7
LTC1273
LTC1275/LTC1276
127356fa
INPUT FREQUENCY (Hz)
10k
0
EFFECTIVE NUMBER OF BITS
3
5
7
10
100k 2M
LTC1273/75/76 • TPC04
1
4
6
9
12
11
8
2
1M
62
56
74
68
50
S/(N + D) (dB)
f
SAMPLE
= 300kHz
ENOBs and S/(N + D)
vs Input Frequency
INPUT FREQUENCY (Hz)
1k
0
SIGNAL-TO-NOISE RATIO (dB)
10k 1M
LTC1273/75/76 • TPC05
80
100k
f
SAMPLE
= 300kHz
70
60
50
40
30
20
10
Signal-to-Noise Ratio (Without
Harmonics) vs Input Frequency Distortion vs Input Frequency
CCHARA TERIST
ICS
UW
AT
Y
P
I
CA
LPER
F
O
R
C
E
CODE
0
1.0
INL ERROR (LSB)
0.5
0
0.5
1.0
512 1024 1536 2048
LTC1273/75/76 • TPC01
2560 3072 3584 4096
Integral Nonlinearity
TEMPERATURE (°C)
–50
0
SUPPLY CURRENT (mA)
10
25
0
50
75
LTC1273/75/76 • TPC03
5
20
15
–25
25
100
125
CODE
0
1.0
DNL ERROR (LSB)
0.5
0
0.5
1.0
512 1024 1536 2048
LTC1273/75/76 • TPC02
2560 3072 3584 4096
Differential Nonlinearity Supply Current vs Temperature
Power Supply Feedthrough
vs Ripple Frequency (LTC1273)
RIPPLE FREQUENCY (Hz)
1k
120
AMPLITUDE OF POWER SUPPLY FEEDTHROUGH (dB)
–40
–20
0
10k 100k 1M
LTC1273/75/76 • TPC07
–60
–80
100
V
DD
(V
RIPPLE
= 1mV)
DGND
(V
RIPPLE
= 0.1V)
f
SAMPLE
= 300kHz
Power Supply Feedthrough
vs Ripple Frequency (LTC1275/76)
RIPPLE FREQUENCY (Hz)
1k
120
AMPLITUDE OF POWER SUPPLY FEEDTHROUGH (dB)
–40
–20
0
10k 100k 1M
LTC1273/75/76 • TPC08
–60
–80
100
f
SAMPLE
= 300kHz
V
DD
(V
RIPPLE
= 1mV)
DGND
(V
RIPPLE
= 0.1V)
V
SS
(V
RIPPLE
= 10mV)
INPUT FREQUENCY (Hz)
–80
AMPLITUDE (dB BELOW THE FUNDAMENTAL)
–60
–40
–20
0
1k 100k 1M 10M
LTC1273/75/76 • TPC06
100
10k
–90
–70
–50
–30
–10
f
SAMPLE
= 300kHz
THD
2nd HARMONIC
3rd HARMONIC
8
LTC1273
LTC1275/LTC1276
127356fa
CCHARA TERIST
ICS
UW
AT
Y
P
I
CA
LPER
F
O
R
C
E
PI FU CTIO S
UU U
A
IN
(Pin 1): Analog Input. 0V to 5V (LTC1273), ±2.5V
(LTC1275) or ±5V (LTC1276).
V
REF
(Pin 2): +2.42V Reference Output. Bypass to
AGND (10µF tantalum in parallel with 0.1µF ceramic).
AGND (Pin 3): Analog Ground.
D11-D4 (Pins 4 to 11): Three-State Data Outputs.
DGND (Pin 12): Digital Ground.
D3/11-D0/8 (Pins 13 to 16): Three-State Data Outputs.
NC (Pins 17 and 18): No Connection.
HBEN (Pin 19): High Byte Enable Input. This pin is used
to multiplex the internal 12-bit conversion result into
the lower bit outputs (D7-D0/8). See Table 1. HBEN also
disables conversion start when HIGH.
RD (Pin 20): READ Input. This active low signal starts
a conversion when CS and HBEN are low. RD also
enables the output drivers when CS is low.
CS (Pin 21): The CHIP SELECT Input must be low for
the ADC to recognize RD and HBEN inputs.
BUSY (Pin 22): The BUSY Output shows the converter
status. It is low when a conversion is in progress.
S/(N + D) vs Input Frequency and
Amplitude
Acquisition Time
vs Source Impedance
Intermodulation Distortion Plot
R
SOURCE
()
10
2500
ACQUISITION TIME (ns)
3000
3500
4000
4500
100 1k 10k
LTC1273/75/76 • TPC10
2000
1500
500
0
1000
INPUT FREQUENCY (Hz)
20
SIGNAL/(NOISE + DISTORTION) (dB)
40
50
70
80
10k 100k 10M
LTC1273/75/76 • TPC11
0
1k
60
30
10
1M
V
IN
= –60dB
V
IN
= –20dB
V
IN
= 0dB
f
SAMPLE
= 300kHz
Spurious Free Dynamic Range
vs Input Frequency
Reference Voltage
vs Load Current
LOAD CURRENT (mA)
–5
2.405
REFERENCE VOLTAGE (V)
2.410
2.415
2.420
2.425
2.430
2.435
–4 –2 –1 2
LTC1273/75/76 • TPC13
–3 0 1
INPUT FREQUENCY (Hz)
10k
–60
SPURIOUS FREE DYNAMIC RANGE (dB)
–50
–40
–30
–20
100k 1M 10M
LTC1273/75/76 • TPC12
–70
–80
–90
100
–10
0
f
SAMPLE
= 300kHz
FREQUENCY (kHz)
0
120
AMPLITUDE (dB)
100
–80
–60
–40
40 80
120
160
LTC1273/75/76 • F05
–20
0
20 60 100
140
f
SAMPLE
= 300kHz
f
IN1
= 29.37kHz
f
IN2
= 32.446kHz
9
LTC1273
LTC1275/LTC1276
127356fa
PI
U
FU
U
C
U
S
O
TI
V
SS
(Pin 23): Negative Supply. –5V for LTC1275/
LTC1276. Bypass to AGND with 0.1µF ceramic.
NC (Pin 23): No Connection for LTC1273.
V
DD
(Pin 24): Positive Supply, 5V. Bypass to AGND
(10µF tantalum in parallel with 0.1µF ceramic).
Table 1. Data Bus Output, CS and RD = LOW
Pin 4 Pin 5 Pin 6 Pin 7 Pin 8 Pin 9 Pin 10 Pin 11 Pin 13 Pin 14 Pin 15 Pin 16
MNEMONIC* D11 D10 D9 D8 D7 D6 D5 D4 D3/11 D2/10 D1/9 D0/8
HBEN = LOW DB11 DB10 DB9 DB8 DB7 DB6 DB5 DB4 DB3 DB2 DB1 DB0
HBEN = HIGH DB11 DB10 DB9 DB8 LOW LOW LOW LOW DB11 DB10 DB9 DB8
*D11...D0/8 are the ADC data output pins.
DB11...DB0 are the 12-bit conversion results, DB11 is the MSB.
FU TIO AL BLOCK DIAGRA
UU W
C
SAMPLE
CONTROL
LOGIC
INTERNAL
CLOCK
SUCCESSIVE
APPROXIMATION
REGISTER
12
12
OUTPUT
LATCHES
D11
D0/8
BUSY
2.42V
REFERENCE
V
REF(OUT)
DGNDAGND
A
IN
SAMPLE
HOLD
SAMPLE
V
SS
(NC ON LTC1273)V
DD
HBEN
CS
RD
LTC1273/75/76 • FBD
12-BIT
CAPACITIVE
DAC
COMPARATOR
+
TEST CIRCUITS
Load Circuits for Access Time
Load Circuits for Output Float Delay
3k
C
L
DBN
DGND
A) HIGH-Z TO V
OH
(t
3
)
AND V
OL
TO V
OH
(t
6
)
C
L
DBN
3k
5V
B) HIGH-Z TO V
OL
(t
3
)
AND V
OH
TO V
OL
(t
6
)
DGND
1273/75/76 • TA07
3k
10pF
DBN
DGND
A) V
OH
TO HIGH-Z
10pF
DBN
3k
5V
B) V
OL
TO HIGH-Z
DGND
1273/75/76 • TA08

LTC1276ACN#PBF

Mfr. #:
Manufacturer:
Analog Devices Inc.
Description:
Analog to Digital Converters - ADC 12-B, 300ksps Smpl A/D Convs w/ Ref
Lifecycle:
New from this manufacturer.
Delivery:
DHL FedEx Ups TNT EMS
Payment:
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