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LTC1273
LTC1275/LTC1276
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TMS320C25
Figure 17 shows an interface between the LTC1273 and
the TMS320C25.
The W/R signal of the DSP initiates a conversion and
conversion results are read from the LTC1273 using the
following instruction:
IN D, PA
where D is Data Memory Address and PA is the PORT
ADDRESS.
Figure 17. TMS320C25 Interface
DATA BUS
LTC1273/75/76 • F17
ADDRESS BUS
D0
D16
R/W
READY
IS
A1
A16
TMS320C25
ADDRESS
DECODE
EN
D0/8
D11
RD
BUSY
CS
HBEN
LTC1273/75/76
ADDITIONAL PINS OMITTED FOR CLARITY
DATA BUS
LTC1273/75/76 • F18
ADDRESS BUS
D0
D11
R/W
DTACK
AS
A1
A23
MC68000
ADDRESS
DECODE
EN
D0/8
D11
RD
BUSY
CS
HBEN
LTC1273/75/76
ADDITIONAL PINS OMITTED FOR CLARITY
Figure 18. MC68000 Interface
8085A/Z80 Microprocessor
Figure 19 shows an LTC1273 interface for the Z80/8085A.
The LTC1273 is operating in the Slow Memory Mode and
a two byte read is required. Not shown in the figure is the
8-bit latch required to demultiplex the 8085A common
address/data bus. A0 is used to assert HBEN so that an
even address (HBEN = LOW) to the LTC1273 will start a
conversion and read the low data byte. An odd address
(HBEN = HIGH) will read the high data byte. This is
accomplished with the single 16-bit LOAD instruction
below.
For the 8085A LHLD (B000)
For the Z80 LDHL, (B000)
Figure 19. 8085A and Z80 Interface
DATA BUS
LTC1273/75/76 • F19
ADDRESS BUS
D0
D7
RD
WAIT
MREQ
A0
A15
Z80
8085A
ADDRESS
DECODE
EN
D0/8
D7
RD
BUSY
CS
HBEN
ADDITIONAL PINS OMITTED FOR CLARITY
LTC1273/75/76
A0
MC68000 Microprocessor
Figure 18 shows a typical interface for the MC68000. The
LTC1273 is operating in the Slow Memory Mode. Assum-
ing the LTC1273 is located at address C000, then the
following single 16-bit MOVE instruction both starts a
conversion and reads the conversion result:
Move.W $C000,D0
At the beginning of the instruction cycle when the ADC
address is selected, BUSY and CS assert DTACK so that
the MC68000 is forced into a WAIT state. At the end of
conversion, BUSY returns high and the conversion result
is placed in the D0 register of the microprocessor.
20
LTC1273
LTC1275/LTC1276
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This is a two byte read instruction which loads the ADC
data (address B000) into the HL register pair. During the
first read operation, BUSY forces the microprocessor to
WAIT for the LTC1273 conversion. No WAIT states are
inserted during the second read operation when the mi-
croprocessor is reading the high data byte.
TMS32010 Microcomputer
Figure 20 shows an LTC1273/TMS32010 interface. The
LTC1273 is operating in the ROM Mode.
The LTC1273 is mapped at a port address. The following
I/O instruction starts a conversion and reads the previous
conversion result into data memory.
IN A,PA (PA = PORT ADDRESS)
When conversion is complete, a second I/O instruction
reads the up-to-date data into memory and starts another
conversion. A delay at least as long as the ADC conversion
time must be allowed between I/O instructions.
MUXing with CD4051
The high input impedance of the LTC1273/LTC1275/
LTC1276 provides an easy, cheap, fast, and accurate way
to multiplex many channels of data through one con-
verter. Figure 21 shows a low cost CD4051 connected to
the LTC1275. The LTC1275’s input draws no DC input
Figure 20. TMS32010 Interface
DATA BUS
LTC1273/75/76 • F20
PORT ADDRESS BUS
D0
D11
DEN
PA0
PA2
TMS32010
ADDRESS
DECODE
EN
D0/8
D11
RD
CS
HBEN
LTC1273/75/76
LINEAR CIRCUITRY OMITTED FOR CLARITY
current so it can be accurately driven by the unbuffered
MUX. The CD4520 counter increments the MUX channel
after each sample is taken. Figure 22 shows the acquisi-
tion time of LTC1275 vs the source resistance. For a
500 maximum “on” resistance of the CD4051, the
acquisition time of the ADC is not greatly affected. For
larger source resistances, modest increases in acquisi-
tion time must be allowed.
V
DD
5V
V
SS
V
EE
ABC
–5V
8 INPUT
CHANNELS
±2.8V
INPUT
VARIES
NO
BUFFER
REQUIRED
D11
D0
CS
RD
BUSY
LTC1275
A
IN
µP
OR
DSP
ENABLE
RESET
Q2
Q1
Q0
CD4520
COUNTER
5V
LTC1273/75/76 • F21
CD4051
Figure 21. MUXing the LTC1275 with CD4051
SOURCE RESISTANCE ()
10
2
ACQUISITION TIME (µs)
3
4
100 1k 10k
LTC1273/75/76 • F22
1
0
LTC1275A
IN
R
SOURCE
V
IN
500
Figure 22. Acqusition Time of LTC1275 vs Source Resistance
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Demodulating a Signal by Undersampling
with LTC1275
Figure 23 shows a 455kHz amplitude modulated input
undersampled by the LTC1275. With a 227.5kHz sample
rate, the converter provides a 100dB noise floor and 68dB
distortion when digitizing the 455kHz AM input.
Figure 24 shows an FFT of the AM signal digitized at
212.5kHz.
A
IN
LTC1275
D11
D0
455kHz
AMPLITUDE
MODULATED
INPUT
RD RD
–5V
227.5kHz
SAMPLE RATE
5V
LTC1273/75/76 • F23
DATA OUTPUT
Figure 23. A 455kHz Amplitude Modulated Input
Undersampled by the LTC1275
FREQUENCY (kHz)
0
110
AMPLITUDE (dB)
–90
–70
–50
–30
20 40 60 80
LTC1273/75/76 • F24
100 120
–10
100
–80
–60
–40
–20
0
f
SAMPLE
= 212.5kHz
f
IN
= 454.8kHz
f
MOD
= 5.03kHz
Figure 24. 455kHz Input Voltage Modulated by a 5kHz Signal
A time domain view of the demodulation is shown in Figure
25. The top trace shows the 455kHz waveform modulated
by a –6dB, 5kHz signal. The bottom trace shows the
demodulated signal produced by the LTC1275 recon-
structed through a 12-bit DAC. The resultant frequency is
5kHz with a sample rate of 227.5kHz. There are roughly 45
points per cycle.
Figure 25. 455kHz AM Signal Demodulated to 10.5 ENOBs
DEMODULATED
5kHz OUTPUT
455kHz
AM SIGNAL
50µs/DIV
LTC1273/75/76 • F27
1V/DIV
1V/DIV
100ps Resolution Time Measurement with LTC1273
Figure 26 shows a circuit that precisely measures the
difference in time between two events. It has a 400ns full
scale and 100ps resolution. The start signal releases the
ramp generator made up of the PNP current source and
the 250pF capacitor. The circuit ramps until the stop
signal shuts off the current source. The final value of the
ramp represents the time between the start and stop
events. The LTC1273 digitizes this final value and outputs
the digital data.

LTC1276ACN#PBF

Mfr. #:
Manufacturer:
Analog Devices Inc.
Description:
Analog to Digital Converters - ADC 12-B, 300ksps Smpl A/D Convs w/ Ref
Lifecycle:
New from this manufacturer.
Delivery:
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