ADP3650JRZ Datasheet ADP3650JRZ, ADP3650JRZ-RL, ADP3650JCPZ-RL | P10-P12

ADP3650

Rev. A | Page 9 of 12

THEORY OF OPERATION

The ADP3650 is optimized for driving two N-channel

MOSFETs in a synchronous buck converter topology. A single

PWM input (IN) signal is all that is required to properly drive

the high-side and the low-side MOSFETs. Each driver is capable

of driving a 3 nF load at speeds up to 500 kHz. A functional

block diagram of the ADP3650 is shown in Figure 1.

LOW-SIDE DRIVER

The low-side driver is designed to drive a ground referenced

N-channel MOSFET. The bias supply to the low-side driver is

internally connected to the VCC supply and PGND.

When the driver is enabled, the driver output is 180° out of

phase with the PWM input. When the ADP3650 is disabled,

the low-side gate is held low.

HIGH-SIDE DRIVER

The high-side driver is designed to drive a floating N-channel

MOSFET. The bias voltage for the high-side driver is developed

by an external bootstrap supply circuit that is connected

between the BST and SW pins.

The bootstrap circuit comprises Diode D1 and Bootstrap

Capacitor C

BST1

. C

BST2

and R

BST

are included to reduce the high-

side gate drive voltage and to limit the switch node slew rate.

When the ADP3650 starts up, the SW pin is at ground, so the

bootstrap capacitor charges up to V

through D1. When the

PWM input goes high, the high-side driver begins to turn on

the high-side MOSFET, Q1, by pulling charge out of C

BST1

and

BST2

. As Q1 turns on, the SW pin rises up to V

and forces the

BST pin to V

+ V

C (BST)

. This holds Q1 on because enough gate-

to-source voltage is provided. To complete the cycle, Q1 is

switched off by pulling the gate down to the voltage at the SW

pin. When the low-side MOSFET, Q2, turns on, the SW pin is

pulled to ground. This allows the bootstrap capacitor to charge

up to VCC again.

The output of the high-side driver is in phase with the PWM

input. When the driver is disabled, the high-side gate is held low.

OVERLAP PROTECTION CIRCUIT

The overlap protection circuit prevents both of the main power

switches, Q1 and Q2, from being on at the same time. This is

done to prevent shoot-through currents from flowing through

both power switches and the associated losses that can occur

during their on/off transitions. The overlap protection circuit

accomplishes this by adaptively controlling the delay from the

Q1 turn-off to the Q2 turn-on and by internally setting the

delay from the Q2 turn-off to the Q1 turn-on.

To prevent the overlap of the gate drives during the Q1 turn-off

and the Q2 turn-on, the overlap circuit monitors the voltage at

the SW pin. When the PWM input signal goes low, Q1 begins

to turn off (after propagation delay). Before Q2 can turn on, the

overlap protection circuit makes sure that SW has first gone

high and then waits for the voltage at the SW pin to fall from

to 1 V. When the voltage on the SW pin falls to 1 V, Q2

begins to turn on. If the SW pin has not gone high first, the Q2

turn-on is delayed by a fixed 150 ns. By waiting for the voltage

on the SW pin to reach 1 V or for the fixed delay time, the

overlap protection circuit ensures that Q1 is off before Q2 turns

on, regardless of variations in temperature, supply voltage, input

pulse width, gate charge, and drive current. If SW does not go

below 1 V after 190 ns, DRVL turns on. This can occur if the

current flowing in the output inductor is negative and flows

through the high-side MOSFET body diode.

ADP3650

Rev. A | Page 10 of 12

APPLICATIONS INFORMATION

SUPPLY CAPACITOR SELECTION

For the supply input (VCC) of the ADP3650, a local bypass

capacitor is recommended to reduce noise and to supply some

of the peak currents that are drawn. Use a 4.7 μF, low ESR

capacitor. Multilayer ceramic chip (MLCC) capacitors provide

the best combination of low ESR and small size. Keep the

ceramic capacitor as close as possible to the ADP3650.

BOOTSTRAP CIRCUIT

The bootstrap circuit uses a charge storage capacitor (C

BST

)

and a diode, as shown in Figure 1. These components can be

selected after the high-side MOSFET is chosen. The bootstrap

capacitor must have a voltage rating that can handle twice the

maximum supply voltage. A minimum 50 V rating is recom-

mended. The capacitor values are determined by

GATE

BST2BST1

CC ×=+ 10 (1)

GATE

BST2BST1

BST1

−

(2)

where:

GATE

is the total gate charge of the high-side MOSFET at V

GATE

is the desired gate drive voltage (usually in the range of

5 V to 10 V, 7 V being typical).

is the voltage drop across D1.

Rearranging Equation 1 and Equation 2 to solve for C

BST1

yields

GATE

BST

−

×= 10

BST2

can then be found by rearranging Equation 1.

BST

GATE

BST2

C −×=

For example, an NTD60N02 has a total gate charge of about

12 nC at V

GATE

= 7 V. Using V

= 12 V and V

= 1 V, then

BST1

= 12 nF and C

BST2

= 6.8 nF. Good quality ceramic capacitors

should be used.

BST

is used to limit slew rate and minimize ringing at the switch

node. It also provides peak current limiting through D1. An

BST

value of 1.5 Ω to 2.2 Ω is a good choice. The resistor needs

to handle at least 250 mW due to the peak currents that flow

through it.

A small signal diode can be used for the bootstrap diode due

to the ample gate drive voltage supplied by V

. The bootstrap

diode must have a minimum 15 V rating to withstand the

maximum supply voltage. The average forward current can

be estimated by

MAX

GATE

AVGF

fQI ×=

)(

(3)

where

MAX

is the maximum switching frequency of the

controller.

The peak surge current rating should be calculated by

BST

PEAKF

−

)(

(4)

MOSFET SELECTION

When interfacing the ADP3650 to external MOSFETs, the

designer should consider ways to make a robust design that

minimizes stresses on both the driver and the MOSFETs. These

stresses include exceeding the short time duration voltage

ratings on the driver pins as well as on the external MOSFET.

It is also highly recommended that the bootstrap circuit be used

to improve the interaction of the driver with the characteristics

of the MOSFETs (see the Bootstrap Circuit section). If a simple

bootstrap arrangement is used, make sure to include a proper

snubber network on the SW node.

HIGH-SIDE (CONTROL) MOSFETS

A high-side, high speed MOSFET is usually selected to

minimize switching losses. This typically implies a low gate

resistance and low input capacitance/charge device. Yet, a

significant source lead inductance can also exist that depends

mainly on the MOSFET package; it is best to contact the

MOSFET vendor for this information.

The ADP3650 DRVH output impedance and the input resistance

of the MOSFETs determine the rate of charge delivery to the

internal capacitance of the gate. This determines the speed at

which the MOSFETs turn on and off. However, because of

potentially large currents flowing in the MOSFETs at the on and

off times (this current is usually larger at turn-off due to ramping

up of the output current in the output inductor), the source lead

inductance generates a significant voltage when the high-side

MOSFETs switch off. This creates a significant drain-source

voltage spike across the internal die of the MOSFETs and can

lead to a catastrophic avalanche. The mechanisms involved in

this avalanche condition are referenced in literature from the

MOSFET suppliers.

ADP3650

Rev. A | Page 11 of 12

The MOSFET vendor should provide a safe operating rating for

maximum voltage slew rate at a given drain current. This allows

the designer to derate for the FET turn-off condition described

in this section. When this specification is obtained, determine

the maximum current expected in the MOSFET by

()

OUT

MAX

OUT

CCDCMAX

VVphaseperII

×−+=

)((5)

where:

MAX

is determined by the voltage controller being used with

the driver. This current is divided roughly equally between

MOSFETs if more than one is used (assume a worst-case

mismatch of 30% for design margin).

OUT

is the output inductor value.

When producing the design, there is no exact method for

calculating the dV/dt due to the parasitic effects in the external

MOSFETs as well as in the PCB. However, it can be measured to

determine whether it is safe. If it appears that the dV/dt is too

fast, an optional gate resistor can be added between DRVH and

the high-side MOSFETs. This resistor slows down the dV/dt,

but it increases the switching losses in the high-side MOSFETs.

The ADP3650 is optimally designed with an internal drive

impedance that works with most MOSFETs to switch them

efficiently, yet minimizes dV/dt. However, some high speed

MOSFETs may require this external gate resistor depending on

the currents being switched in the MOSFET.

LOW-SIDE (SYNCHRONOUS) MOSFETS

The low-side MOSFETs are usually selected to have a low on

resistance to minimize conduction losses. This usually implies a

large input gate capacitance and gate charge. The first concern is

to make sure that the power delivery from the ADP3650 DRVL

does not exceed the thermal rating of the driver.

The next concern for the low-side MOSFETs is to prevent

them from being inadvertently switched on when the high-side

MOSFET turns on. This occurs due to the drain-gate capacitance

(Miller capacitance, also specified as C

rss

) of the MOSFET. When

the drain of the low-side MOSFET is switched to VCC by the

high-side MOSFET turning on (at a dV/dt rate), the internal

gate of the low-side MOSFET is pulled up by an amount roughly

equal to V

× (C

rss

iss

). It is important to make sure that this

does not put the MOSFET into conduction.

Another consideration is the nonoverlap circuitry of the

ADP3650 that attempts to minimize the nonoverlap period.

During the state of the high-side MOSFET turning off to the

low-side MOSFET turning on, the SW pin is monitored (as well

as the conditions of SW prior to switching) to adequately

prevent overlap.

However, during the low-side turn-off to high-side turn-on,

the SW pin does not contain information for determining

the proper switching time, so the state of the DRVL pin is

monitored to go below one-sixth of V

; then, a delay is added.

Due to the Miller capacitance and internal delays of the low-

side MOSFET gate, ensure that the Miller-to-input capacitance

ratio is low enough, and that the low-side MOSFET internal

delays are not so large as to allow accidental turn-on of the

low-side MOSFET when the high-side MOSFET turns on.

PCB LAYOUT CONSIDERATIONS

Use the following general guidelines when designing printed

circuit boards. Figure 15 shows an example of the typical land

patterns based on these guidelines.

• Trace out the high current paths and use short, wide

(>20 mil) traces to make these connections.

• Minimize trace inductance between the DRVH and DRVL

outputs and the MOSFET gates.

• Connect the PGND pin of the ADP3650 as close as

possible to the source of the lower MOSFET.

• Locate the VCC bypass capacitor as close as possible to

the VCC and PGND pins.

• When possible, use vias to other layers to maximize

thermal conduction away from the IC.

BST2

BST1

BST

VCC

07826-015

Figure 15. External Component Placement Example

P1-P3 P4-P6 P7-P9 P10-P12 P13-P13

ADP3650JRZ

Mfr. #:

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Manufacturer:

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Description:

Gate Drivers Dual Bootstrapped 12V MOSFET Dvr

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ADP3650JRZ

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