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9FG1200DF-1LF

P1-P3P4-P6P7-P9P10-P12P13-P15P16-P18P19-P21P22-P23
IDT
®
Frequency Gearing Clock for CPU, PCIe Gen1, Gen2 & FBD 1138C 02/08/10
ICS9FG1200D-1
16
SMBus Table: Gear PLL Frequency Control Register
Pin # Name Control Function T
yp
e0 1 PWD
Bit 7
Gear PLL N Div7 RW X
Bit 6
Gear PLL N Div6 RW X
Bit 5
Gear PLL N Div5 RW X
Bit 4
Gear PLL N Div4 RW X
Bit 3
Gear PLL N Div3 RW X
Bit 2
Gear PLL N Div2 RW X
Bit 1
Gear PLL N Div1 RW X
Bit 0
Gear PLL N Div0 RW X
SMBusTable: Gear PLL Output Divider Register
Pin # Name Control Function T
yp
e0 1 PWD
Bit 7
0
Bit 6
0
Bit 5
0
Bit 4
0
Bit 3
GoutDiv 3
RW
X
Bit 2
GoutDiv 2
RW
X
Bit 1
GoutDiv 1
RW
X
Bit 0
GoutDiv 1
RW
X
SMBusTable: Reserved Register
Pin # Name Control Function T
yp
e0 1 PWD
Bit 7
0
Bit 6
0
Bit 5
0
Bit 4
0
Bit 3
0
Bit 2
0
Bit 1
0
Bit 0
0
SMBusTable: Reserved Register
Pin # Name Control Function T
yp
e0 1 PWD
Bit 7
0
Bit 6
0
Bit 5
0
Bit 4
0
Bit 3
0
Bit 2
0
Bit 1
0
Bit 0
0
RESERVED
RESERVED
RESERVED
RESERVED
RESERVED
RESERVED
RESERVED
RESERVED
B
y
te 12
-
N Divider Programming
bits
RESERVED
Contact IDT for 9FG1200-
1 M/N programming Table
-
-
-
-
-
-
Contact IDT for Output
Divider Table
RESERVED
RESERVED
RESERVED
B
y
te 15
RESERVED
RESERVED
RESERVED
-
B
y
te 13
B
y
te 14
RESERVED
RESERVED
Gear Output Divider
RESERVED
RESERVED
RESERVED
IDT
®
Frequency Gearing Clock for CPU, PCIe Gen1, Gen2 & FBD 1138C 02/08/10
ICS9FG1200D-1
17
SMBusTable: Reserved Register
Pin # Name Control Function T
yp
e0 1 PWD
Bit 7
0
Bit 6
0
Bit 5
0
Bit 4
0
Bit 3
0
Bit 2
0
Bit 1
0
Bit 0
0
SMBus Table: 1:1 PLL Frequency Control Register
Pin # Name Control Function T
yp
e0 1 PWD
Bit 7
0
Bit 6
0
Bit 5
1:1 PLL M Div5 RW X
Bit 4
1:1 PLL M Div4 RW X
Bit 3
1:1 PLL M Div3 RW X
Bit 2
1:1 PLL M Div2 RW X
Bit 1
1:1 PLL M Div1 RW X
Bit 0
1:1 PLL M Div0 RW X
SMBus Table: 1:1 PLL Frequency Control Register
Pin # Name Control Function T
yp
e0 1 PWD
Bit 7
1:1 PLL N Div7 RW X
Bit 6
1:1 PLL N Div6 RW X
Bit 5
1:1 PLL N Div5 RW X
Bit 4
1:1 PLL N Div4 RW X
Bit 3
1:1 PLL N Div3 RW X
Bit 2
1:1 PLL N Div2 RW X
Bit 1
1:1 PLL N Div1 RW X
Bit 0
1:1 PLL N Div0 RW X
SMBusTable: 1:1 PLL Output Divider Register
Pin # Name Control Function T
yp
e0 1 PWD
Bit 7
0
Bit 6
0
Bit 5
0
Bit 4
0
Bit 3
1outDiv 3
RW
X
Bit 2
1outDiv 2
RW
X
Bit 1
1outDiv 1
RW
X
Bit 0
1outDiv 1
RW
X
RESERVED
RESERVED
RESERVED
RESERVED
N Divider Programming
bits
Contact IDT for 9FG1200-
1 M/N programming Table
RESERVED
RESERVED
RESERVED
Contact IDT for 9FG1200-
1 M/N programming Table
-
-
-
-
-
-
-
-
-
B
y
te 18
B
y
te 17
-
B
y
te 19
-
-
-
-
B
y
te 16
M Divider Programming
bits
RESERVED
RESERVED
RESERVED
RESERVED
RESERVED
1:1 Output Divider
Contact IDT for Output
Divider Table
RESERVED
RESERVED
IDT
®
Frequency Gearing Clock for CPU, PCIe Gen1, Gen2 & FBD 1138C 02/08/10
ICS9FG1200D-1
18
SMBusTable: Reserved Register
Pin # Name Control Function T
yp
e0 1 PWD
Bit 7
0
Bit 6
0
Bit 5
0
Bit 4
0
Bit 3
0
Bit 2
0
Bit 1
0
Bit 0
0
SMBusTable: Test Byte Register
Test T
yp
ePWD
Bit 7
RW 0
Bit 6
RW 0
Bit 5
RW 0
Bit 4
RW 0
Bit 3
RW 0
Bit 2
RW 0
Bit 1
RW 0
Bit 0
RW 0
Note: Do NOT write to Bit 21. Erratic device operation will result!
RESERVED
RESERVED
RESERVED
RESERVED
B
y
te 20
RESERVED
RESERVED
B
y
te 21 Test Function
RESERVED
RESERVED
Test Resul
t
` ICS ONLY TEST Reserved
ICS ONLY TEST Reserved
ICS ONLY TEST Reserved
ICS ONLY TEST Reserved
ICS ONLY TEST Reserved
ICS ONLY TEST Reserved
ICS ONLY TEST Reserved
ICS ONLY TEST Reserved
P1-P3P4-P6P7-P9P10-P12P13-P15P16-P18P19-P21P22-P23

9FG1200DF-1LF

Mfr. #:
Buy 9FG1200DF-1LF
Manufacturer:
IDT
Description:
Clock Buffer PCIE GEARING BUFFER - GEN2
Lifecycle:
New from this manufacturer.
Delivery:
DHL FedEx Ups TNT EMS
Payment:
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