IDT
®
Frequency Gearing Clock for CPU, PCIe Gen1, Gen2 & FBD 1138C 02/08/10
ICS9FG1200D-1
4
Pin Description (continued)
PIN # PIN NAME T
ePin Descri
tion
29 SMBCLK IN Clock pin of SMBUS circuitry, 5V tolerant
30 SMB_A2_PLLBYP# IN
SMBus address bit 2. When Low, the part operates as a fanout buffer
with the PLL bypassed. When High, the part operates as a zero-delay
buffer (ZDB) with the PLL operating.
0 = fanout mode (PLL bypassed), 1 = ZDB mode (PLL used)
31 OE6# IN
Active low input for enabling DIF pair 6.
1 = tri-state outputs, 0 = enable outputs
32 DIF_6# OUT 0.7V differential complement clock output
33 DIF_6 OUT 0.7V differential true clock output
34 OE7# IN
Active low input for enabling DIF pair 7.
1 = tri-state outputs, 0 = enable outputs
35 DIF_7# OUT 0.7V differential complement clock output
36 DIF_7 OUT 0.7V differential true clock output
37 GND PWR Ground pin.
38 VDD PWR Power supply, nominal 3.3V
39 DIF_8# OUT 0.7V differential complement clock output
40 DIF_8 OUT 0.7V differential true clock output
41 OE8# IN
Active low input for enabling DIF pair 8.
1 = tri-state outputs, 0 = enable outputs
42 DIF_9# OUT 0.7V differential complement clock output
43 DIF_9 OUT 0.7V differential true clock output
44 OE9# IN
Active low input for enabling DIF pair 9.
1 = tri-state outputs, 0 = enable outputs
45 VTT_PWRGD#/PD IN
Vtt_PwrGd# is an active low input used to determine when latched
inputs are ready to be sampled. PD is an asynchronous active high
input pin used to put the device into a low power state. The internal
clocks, PLLs and the crystal oscillator are stopped.
46 FS_A_410 IN
3.3V tolerant low threshold input for CPU frequency selection. This
pin requires CK410 FSA. Refer to input electrical characteristics for
Vil_FS and Vih_FS threshold values.
47 DIF_10# OUT 0.7V differential complement clock output
48 DIF_10 OUT 0.7V differential true clock output
49 GND PWR Ground pin.
50 VDD PWR Power supply, nominal 3.3V
51 DIF_11# OUT 0.7V differential complement clock output
52 DIF_11 OUT 0.7V differential true clock output
53 OE10_11# IN
Active low input for enabling output pairs 10 and 11.
1 = tri-state outputs, 0 = enable outputs
54 IREF OUT
This pin establishes the reference current for the differential current-
mode output pairs. This pin requires a fixed precision resistor tied to
ground in order to establish the appropriate current. 475 ohms is the
standard value.
55 GNDA PWR Ground pin for the PLL core.
56 VDDA PWR 3.3V power for the PLL core.
