CAT25010, CAT25020, CAT25040
www.onsemi.com
10
Hold Operation
The HOLD input can be used to pause communication
between host and CAT25010/20/40. To pause, HOLD
must
be taken low while SCK is low (Figure 11). During the hold
condition the device must remain selected (CS
low). During
the pause, the data output pin (SO) is tristated (high
impedance) and SI transitions are ignored. To resume
communication, HOLD
must be taken high while SCK is low.
Design Considerations
The CAT25010/20/40 devices incorporate PowerOn
Reset (POR) circuitry which protects the internal logic
against powering up in the wrong state. The device will
power up into Standby mode after V
CC
exceeds the POR
trigger level and will power down into Reset mode when
V
CC
drops below the POR trigger level. This bidirectional
POR behavior protects the device against ‘brownout’
failure following a temporary loss of power.
The CAT25010/20/40 device powers up in a write disable
state and in a low power standby mode. A WREN instruction
must be issued prior to any writes to the device.
After power up, the CS
pin must be brought low to enter
a ready state and receive an instruction. After a successful
byte/page write or status register write, the device goes into
a write disable mode. The CS
input must be set high after the
proper number of clock cycles to start the internal write
cycle. Access to the memory array during an internal write
cycle is ignored and programming is continued. Any invalid
opcode will be ignored and the serial output pin (SO) will
remain in the high impedance state.
Figure 11. HOLD Timing
SCK
SO
HIGH IMPEDANCE
Dashed Line = mode (1, 1)
t
LZ
CS
HOLD
t
CD
t
HD
t
HD
t
CD
t
HZ
ORDERING INFORMATION
Device Order Number
Specific
Device
Marking
(Note 14)
Package Type Temperature Range Lead Finish Shipping
CAT25010HU4IGT3 S0U UDFN8EP 40°C to +85°C NiPdAu 3,000 Units / Tape & Reel
CAT25010VIGT3 25010E SOIC8, JEDEC 40°C to +125°C NiPdAu 3,000 Units / Tape & Reel
CAT25010YIGT3 S01E TSSOP8 40°C to +85°C NiPdAu 3,000 Units / Tape & Reel
CAT25020HU4IGT3 S1U UDFN8EP 40°C to +85°C NiPdAu 3,000 Units / Tape & Reel
CAT25020VIGT3 25020E SOIC8, JEDEC 40°C to +125°C NiPdAu 3,000 Units / Tape & Reel
CAT25020YIGT3 S02E TSSOP8 40°C to +85°C NiPdAu 3,000 Units / Tape & Reel
CAT25040HU4IGT3 S2U UDFN8EP 40°C to +85°C NiPdAu 3,000 Units / Tape & Reel
CAT25040VIGT3 25040E SOIC8, JEDEC 40°C to +85°C NiPdAu 3,000 Units / Tape & Reel
CAT25040YIGT3 S04E TSSOP8 40°C to +85°C NiPdAu 3,000 Units / Tape & Reel
For information on tape and reel specifications, including part orientation and tape sizes, please refer to our Tape and Reel Packaging Specifi-
cations Brochure, BRD8011/D.
14.Specific Device Marking shows the first row top marking for new product (Revision E).
15.All packages are RoHScompliant (Leadfree, Halogenfree).
16.The standard lead finish is NiPdAu.
17.For detailed information and a breakdown of device nomenclature and numbering systems, please see the ON Semiconductor Device
Nomenclature document, TND310/D, available at www.onsemi.com
UDFN8, 2x3 EXTENDED PAD
CASE 517AZ
ISSUE A
DATE 23 MAR 201
5
SCALE 2:1
NOTES:
1. DIMENSIONING AND TOLERANCING PER
ASME Y14.5M, 1994.
2. CONTROLLING DIMENSION: MILLIMETERS.
3. DIMENSION b APPLIES TO PLATED
TERMINAL AND IS MEASURED BETWEEN
0.15 AND 0.25MM FROM THE TERMINAL TIP.
4. COPLANARITY APPLIES TO THE EXPOSED
PAD AS WELL AS THE TERMINALS.
A
D
E
B
C0.10
PIN ONE
REFERENCE
TOP VIEW
SIDE VIEW
BOTTOM VIEW
L
D2
E2
C
C0.10
C0.08
A1
SEATING
PLANE
NOTE 3
b
8X
0.10 C
0.05 C
A
B
DIM MIN MAX
MILLIMETERS
A 0.45 0.55
A1 0.00 0.05
b 0.20 0.30
D 2.00 BSC
D2 1.35 1.45
E 3.00 BSC
E2 1.25 1.35
e 0.50 BSC
L 0.25 0.35
1
4
8
*For additional information on our Pb−Free strategy and soldering
details, please download the ON Semiconductor Soldering and
Mounting Techniques Reference Manual, SOLDERRM/D.
SOLDERING FOOTPRINT*
0.50
PITCH
1.45
3.40
1
DIMENSIONS: MILLIMETERS
1
NOTE 4
0.30
8X
DETAIL A
A3 0.13 REF
A3
A
DETAIL B
L1
DETAIL A
L
ALTERNATE
CONSTRUCTIONS
L
L1 −− 0.15
e
RECOMMENDED
5
1.56
GENERIC
MARKING DIAGRAM*
XXXXX = Specific Device Code
A = Assembly Location
WL = Wafer Lot
Y = Year
W = Work Week
G = Pb−Free Package
*This information is generic. Please refer to
device data sheet for actual part marking.
Pb−Free indicator, “G” or microdot “ G”,
may or may not be present.
XXXXX
AWLYWG
1
M
M
0.68
C0.10
8X
DETAIL B
MOLD CMPDEXPOSED Cu
ALTERNATE
CONSTRUCTIONS
A1
A3
MECHANICAL CASE OUTLINE
PACKAGE DIMENSIONS
http://onsemi.com
1
© Semiconductor Components Industries, LLC, 2002
October, 2002 − Rev. 0
Case Outline Number:
XXX
DOCUMENT NUMBER:
STATUS:
REFERENCE:
DESCRIPTION:
98AON42552E
ON SEMICONDUCTOR STANDARD
UDFN8, 2X3 EXTENDED PAD
Electronic versions are uncontrolled except when
accessed directly from the Document Repository. Printed
versions are uncontrolled except when stamped
“CONTROLLED COPY” in red.
PAGE 1 OF 2
DOCUMENT NUMBER:
98AON42552E
PAGE 2 OF 2
ISSUE REVISION DATE
O RELEASED FOR PRODUCTION FROM POD #UDFN8−046−01 TO ON SEMICON-
DUCTOR. REQ. BY B. BERGMAN.
23 JUL 2009
A REDREW PACKAGE DRAWING TO ON SEMICONDUCTOR/JEDEC STANDARD.
REQ. BY B. BECKER.
23 MAR 2015
© Semiconductor Components Industries, LLC, 2015
March, 2015 − Rev. A
Case Outline Number
:
517AZ
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“Typical” parameters which may be provided in SCILLC data sheets and/or specifications can and do vary in different applications and actual performance may vary over time. All
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CAT25020YI-G

Mfr. #:
Manufacturer:
ON Semiconductor
Description:
EEPROM (256x8) 2K 2.5-5.5
Lifecycle:
New from this manufacturer.
Delivery:
DHL FedEx Ups TNT EMS
Payment:
T/T Paypal Visa MoneyGram Western Union