CAT25010, CAT25020, CAT25040
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9
READ OPERATIONS
Read from Memory Array
To read from memory, the host sends a READ instruction
followed by a 8−bit address (for the CAT25040, bit 3 of the
read instruction opcode contains A8 address bit).
After receiving the last address bit, the CAT25010/20/40
will respond by shifting out data on the SO pin (as shown in
Figure 9). Sequentially stored data can be read out by simply
continuing to run the clock. The internal address pointer is
automatically incremented to the next higher address as data
is shifted out. After reaching the highest memory address,
the address counter “rolls over” to the lowest memory
address, and the read cycle can be continued indefinitely.
The read operation is terminated by taking CS
high.
Read Status Register
To read the status register, the host simply sends a RDSR
command. After receiving the last bit of the command, the
CAT25010/20/40 will shift out the contents of the status
register on the SO pin (Figure 10). The status register may
be read at any time, including during an internal write cycle.
While the internal write cycle is in progress, the RDSR
command will output the full content of the status register
(New product, Rev. E) or the RDY (Ready) bit only (i.e.,
data out = FFh) for previous product revisions C, D (Mature
product). For easy detection of the internal write cycle
completion, both during writing to the memory array and to
the status register, we recommend sampling the RDY bit
only through the polling routine. After detecting the RDY bit
“0”, the next RDSR instruction will always output the
expected content of the status register.
Figure 9. READ Timing
SCK
SI
SO
BYTE ADDRESS
0123456789
D7
D6 D5 D4 D3 D2 D1 D0
DATA OUT
MSB
HIGH IMPEDANCE
OPCODE
1312 14 15 16 17 18 19 20 21 22
00 00X*0 11
Dashed Line = mode (1, 1)
* X = 0 for CAT25010, CAT25020. X = A8 for CAT25040
A
0
A
7
CS
Figure 10. RDSR Timing
012345678 10911121314
SCK
SI
DATA OUT
MSB
HIGH IMPEDANCE
OPCODE
SO
7 6
5
4 3 2 1 0
00000 101
Dashed Line = mode (1, 1)
CS
