NB100LVEP222
www.onsemi.com
8
Table 8. AC CHARACTERISTICS V
CC
= V
CC0
= 2.375 to 3.8 V; V
EE
= 0.0 V or V
CC
= V
CC0
= 0.0 V; V
EE
= −2.375 to −3.8 V
(Note 14)
Symbo
Characteristic
−40°C 25°C 85°C
Uni
Min Typ Max Min Typ Max Min Typ Max
V
Opp
Differential Output Voltage
(Figure 5) f
out
= 50 MHz
f
out
= 0.8 GHz
f
out
= 1.0 GHz
500
550
500
600
650
650
500
525
425
600
650
650
500
500
400
600
650
600
mV
t
PLH
t
PHL
Propagation Delay (Differential Configuration)
CLKx−Q
X
MR−Q
XX
650
700
800
900
900
1200
700
700
875
900
1000
1200
850
700
975
900
1150
1200
ps
t
skew
Within−Device Skew (Note 15)
(÷1 Mode) − Qa[0:1]
− Qb[0:2]
− Qc[0:3]
− Qd[0:5]
− Qa
N
, Qb
N
, Qd
N
− All Outputs
10
10
20
10
10
20
40
40
60
40
40
60
10
10
20
10
10
20
40
40
60
40
40
60
10
10
20
10
10
20
40
40
60
40
40
60
ps
t
skew
Within−Device Skew (Note 15)
(÷2 Mode) − Qa[0:1]
− Qb[0:2]
− Qc[0:3]
− Qd[0:5]
− Qa
N
, Qb
N
, Qd
N
− All Outputs
15
15
20
15
15
20
70
70
70
70
70
70
10
10
20
10
10
20
40
40
50
40
40
50
15
10
15
15
15
15
70
40
70
70
70
70
ps
t
skew
Device−to−Device Skew (Differential
Configuration) (Note 16)
85 300 85 300 85 300 ps
t
JITTER
Random Clock Jitter (Figure 5) (RMS) 1 5 1 4 1 5 ps
V
PP
Input Swing (Differential Configuration)
(Note 17) (Figure 6)
150 800 1200 150 800 1200 150 800 1200 mV
DCO Output Duty Cycle 49.5 50 50.5 49.5 50 50.5 49.5 50 50.5 %
t
r
/t
f
Output Rise/Fall Time 20%−80% 100 200 300 100 200 300 150 250 350 ps
NOTE: Device will meet the specifications after thermal equilibrium has been established when mounted in a test socket or printed circuit
board with maintained transverse airflow greater than 500 lfpm.
14.Measured with LVPECL 750 mV source, 50% duty cycle clock source. All outputs loaded with 50 W to V
CC
/V
CC0
− 2.0 V.
15.Skew is measured between outputs under identical transitions and operating conditions.
16.Device−to−Device skew for identical transitions at identical V
CC
/V
CC0
levels.
17.V
PP
is the differential configuration input voltage swing required to maintain AC characteristics including t
PD
and device−to−device skew.
Figure 5. Output Voltage (V
OPP
) versus Input Frequency and Random Clock Jitter (t
JITTER
) @ 255C
INPUT FREQUENCY (GHz)
0.1 1.5
900
800
700
600
500
400
300
200
V
OPP
, OUTPUT VOLTAGE (mV)
9.0
8.0
7.0
6.0
10
5.0
4.0
3.0
2.0
1.0
0
RMS JITTER (ps)
1.0 2.0
Q AMP (÷ 2)
Q AMP (÷ 1)
RMS JITTER
0.5
