IDD Specifications
Table 8: DDR2 I
DD
Specifications and Conditions – 2GB
Values shown for MT47H256M8THN DDR2 SDRAM only and are computed from values specified in the 2Gb TwinDie (256
Meg x 8) component data sheet
Parameter
Combined
Symbol -80E -667 Units
Operating one bank active-precharge current:
t
CK =
t
CK (I
DD
),
t
RC =
t
RC
(I
DD
),
t
RAS =
t
RAS MIN (I
DD
); CKE is HIGH, S# is HIGH between valid commands;
Address bus inputs are switching; Data bus inputs are switching
I
CDD0
918 873 mA
Operating one bank active-read-precharge current: I
OUT
= 0mA; BL = 4, CL
= CL (I
DD
), AL = 0;
t
CK =
t
CK (I
DD
),
t
RC =
t
RC (I
DD
),
t
RAS =
t
RAS MIN (I
DD
),
t
RCD =
t
RCD (I
DD
); CKE is HIGH, S# is HIGH between valid commands; Address bus inputs
are switching; Data pattern is same as I
DD4W
I
CDD1
1098 1008 mA
Precharge power-down current: All device banks idle;
t
CK =
t
CK (I
DD
); CKE is
LOW; Other control and address bus inputs are stable; Data bus inputs are floating
I
CDD2P
126 126 mA
Precharge quiet standby current: All device banks idle;
t
CK =
t
CK (I
DD
); CKE is
HIGH, S# is HIGH; Other control and address bus inputs are stable; Data bus in-
puts are floating
I
CDD2Q
513 423 mA
Precharge standby current: All device banks idle;
t
CK =
t
CK (I
DD
); CKE is HIGH,
S# is HIGH; Other control and address bus inputs are switching; Data bus inputs
are switching
I
CDD2N
558 468 mA
Active power-down current: All device banks open;
t
CK =
t
CK
(I
DD
); CKE is LOW; Other control and address bus inputs are stable;
Data bus inputs are floating
Fast PDN
exit
MR[12] = 0
I
CDD3P
333 333 mA
Slow PDN
exit
MR[12] = 1
153 153
Active standby current: All device banks open;
t
CK =
t
CK (I
DD
),
t
RAS =
t
RAS
MAX (I
DD
),
t
RP =
t
RP (I
DD
); CKE is HIGH, S# is HIGH between valid commands;
Other control and address bus inputs are switching; Data bus inputs are switching
I
CDD3N
648 603 mA
Operating burst write current: All device banks open; Continuous burst
writes; BL = 4, CL = CL (I
DD
), AL = 0;
t
CK =
t
CK (I
DD
),
t
RAS =
t
RAS MAX (I
DD
),
t
RP =
t
RP (I
DD
); CKE is HIGH, S# is HIGH between valid commands; Address bus inputs
are switching; Data bus inputs are switching
I
CDD4W
1548 1323 mA
Operating burst read current: All device banks open; Continuous burst read,
I
OUT
= 0mA; BL = 4, CL = CL (I
DD
), AL = 0;
t
CK =
t
CK (I
DD
),
t
RAS =
t
RAS MAX (I
DD
),
t
RP =
t
RP (I
DD
); CKE is HIGH, S# is HIGH between valid commands; Address bus
inputs are switching; Data bus inputs are switching
I
CDD4R
1548 1323 mA
Burst refresh current:
t
CK =
t
CK (I
DD
); REFRESH command at every
t
RFC (I
DD
)
interval; CKE is HIGH, S# is HIGH between valid commands; Other control and
address bus inputs are switching; Data bus inputs are switching
I
CDD5
2223 2043 mA
Self refresh current: CK and CK# at 0V; CKE ≤ 0.2V; Other control and address
bus inputs are floating; Data bus inputs are floating
I
CDD6
126 126 mA
2GB (x72, ECC, DR) 200-Pin DDR2 SDRAM SORDIMM
IDD Specifications
PDF: 09005aef83f287c1
hts18c256x72rhz.pdf - Rev. A 3/10 EN
10
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