ADSP-2183
–16– REV. C
Parameter Min Max Unit
Memory Read
Timing Requirements:
t
RDD
RD Low to Data Valid 0.5t
CK
– 8 + w ns
t
AA
A0–A13, xMS to Data Valid 0.75t
CK
– 10.5 + w ns
t
RDH
Data Hold from RD High 0 ns
Switching Characteristics:
t
RP
RD Pulsewidth 0.5t
CK
– 5 + w ns
t
CRD
CLKOUT High to RD Low 0.25t
CK
– 2 0.25t
CK
+ 7 ns
t
ASR
A0–A13, xMS Setup before RD Low 0.25t
CK
– 4 ns
t
RDA
A0–A13, xMS Hold after RD Deasserted 0.25t
CK
– 3 ns
t
RWR
RD High to RD or WR Low 0.5t
CK
– 5 ns
w = wait states × t
CK
.
xMS = PMS, DMS, CMS, IOMS , BMS.
CLKOUT
A0 A13
D
t
RDA
t
RWR
t
RP
t
ASR
t
CRD
t
RDD
t
AA
t
RDH
DMS, PMS,
BMS, IOMS,
CMS
RD
WR
Figure 11. Memory Read
ADSP-2183
–17–
REV. C
Parameter Min Max Unit
Memory Write
Switching Characteristics:
t
DW
Data Setup before WR High 0.5t
CK
– 7 + w ns
t
DH
Data Hold after WR High 0.25t
CK
– 2 ns
t
WP
WR Pulsewidth 0.5t
CK
– 5 + w ns
t
WDE
WR Low to Data Enabled 0 ns
t
ASW
A0–A13, xMS Setup before WR Low 0.25t
CK
– 4 ns
t
DDR
Data Disable before WR or RD Low 0.25t
CK
– 4 ns
t
CWR
CLKOUT High to WR Low 0.25t
CK
– 2 0.25 t
CK
+ 7 ns
t
AW
A0–A13, xMS, Setup before WR Deasserted 0.75t
CK
– 9 + w ns
t
WRA
A0–A13, xMS Hold after WR Deasserted 0.25t
CK
– 3 ns
t
WWR
WR High to RD or WR Low 0.5t
CK
– 5 ns
w = wait states × t
CK
.
xMS = PMS, DMS, CMS, IOMS , BMS.
CLKOUT
A0A13
D
t
WP
t
AW
t
CWR
t
DH
t
WDE
t
DW
t
ASW
t
WWR
t
WRA
t
DDR
DMS, PMS,
BMS, CMS,
IOMS
RD
WR
Figure 12. Memory Write
ADSP-2183
–18– REV. C
Parameter Min Max Unit
Serial Ports
Timing Requirements:
t
SCK
SCLK Period 38 ns
t
SCS
DR/TFS/RFS Setup before SCLK Low 4 ns
t
SCH
DR/TFS/RFS Hold after SCLK Low 7 ns
t
SCP
SCLK
IN
Width 15 ns
Switching Characteristics:
t
CC
CLKOUT High to SCLK
OUT
0.25t
CK
0.25t
CK
+ 10 ns
t
SCDE
SCLK High to DT Enable 0 ns
t
SCDV
SCLK High to DT Valid 15 ns
t
RH
TFS/RFS
OUT
Hold after SCLK High 0 ns
t
RD
TFS/RFS
OUT
Delay from SCLK High 15 ns
t
SCDH
DT Hold after SCLK High 0 ns
t
TDE
TFS (Alt) to DT Enable 0 ns
t
TDV
TFS (Alt) to DT Valid 14 ns
t
SCDD
SCLK High to DT Disable 15 ns
t
RDV
RFS
(Multichannel, Frame Delay Zero) to DT Valid 15 ns
CLKOUT
SCLK
TFS
RFS
DT
ALTERNATE
FRAME MODE
t
CC
t
CC
t
SCS
t
SCH
t
RH
t
SCDE
t
SCDH
t
SCDD
t
TDE
t
RDV
MULTICHANNEL MODE,
FRAME DELAY 0
(MFD = 0)
DR
TFS
IN
RFS
IN
RFS
OUT
TFS
OUT
t
TDV
t
SCDV
t
RD
t
SCP
t
SCK
t
SCP
Figure 13. Serial Ports

ADSP-2183KCAZ-210

Mfr. #:
Manufacturer:
Analog Devices Inc.
Description:
Digital Signal Processors & Controllers - DSP, DSC 16B 52 MIPS 3.3V 2 Serial Prts Host Prt
Lifecycle:
New from this manufacturer.
Delivery:
DHL FedEx Ups TNT EMS
Payment:
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