ADSP-2183
–2– REV. C
This takes place while the processor continues to:
• Receive and transmit data through the two serial ports
• Receive and/or transmit data through the internal DMA port
• Receive and/or transmit data through the byte DMA port
• Decrement timer
Development System
The ADSP-2100 Family Development Software, a complete
set of tools for software and hardware system development,
supports the ADSP-2183. The assembler has an algebraic syntax
that is easy to program and debug. The linker combines object
files into an executable file. The simulator provides an interactive
instruction-level simulation with a reconfigurable user interface
to display different portions of the hardware environment.
The EZ-KIT Lite is a hardware/software kit offering a com-
plete development environment for the ADSP-21xx family:
an ADSP-2189M evaluation board with PC monitor software
plus Assembler, Linker, Simulator and PROM Splitter software.
The ADSP-2189M evaluation board is a low-cost, easy to use
hardware platform on which you can quickly get started with
your DSP software design. The EZ-KIT Lite include the
following features:
• 35.7 MHz ADSP-2189M
• Full 16-bit Stereo Audio I/O with AD73322
CODEC
• RS-232 Interface
• EZ-ICE Connector for Emulator Control
• DSP Demo Programs
• Evaluation Suite of VisualDSP
The ADSP-218x EZ-ICE
®
Emulator aids in the hardware debug-
ging of ADSP-218x systems. The ADSP-218x integrates on-chip
emulation support with a 14-pin ICE-Port interface. This inter-
face provides a simpler target board connection requiring fewer
mechanical clearance considerations than other ADSP-2100
Family EZ-ICEs. The ADSP-218x device need not be removed
from the target system when using the EZ-ICE, nor are any
adapters needed. Due to the small footprint of the EZ-ICE
connector, emulation can be supported in final board designs.
The EZ-ICE performs a full range of functions, including:
• In-target operation
• Up to 20 breakpoints
• Single-step or full-speed operation
• Registers and memory values can be examined and altered
• PC upload and download functions
• Instruction-level emulation of program booting and execution
• Complete assembly and disassembly of instructions
• C source-level debugging
(See Designing An EZ-ICE-Compatible Target System section
of this data sheet for exact specifications of the EZ-ICE target
board connector.)
Additional Information
This data sheet provides a general overview of ADSP-2183
functionality. For additional information on the architecture and
instruction set of the processor, refer to the ADSP-2100 Family
User’s Manual, Third Edition. For more information about the
development tools, refer to the ADSP-2100 Family Development
Tools Data Sheet.
ARCHITECTURE OVERVIEW
The ADSP-2183 instruction set provides flexible data moves
and multifunction (one or two data moves with a computation)
instructions. Every instruction can be executed in a single pro-
cessor cycle. The ADSP-2183 assembly language uses an alge-
braic syntax for ease of coding and readability. A comprehensive
set of development tools supports program development.
Figure 1 is an overall block diagram of the ADSP-2183. The
processor contains three independent computational units: the
ALU, the multiplier/accumulator (MAC) and the shifter. The
computational units process 16-bit data directly and have provi-
sions to support multiprecision computations. The ALU per-
forms a standard set of arithmetic and logic operations; division
primitives are also supported. The MAC performs single-cycle
multiply, multiply/add and multiply/subtract operations with
40 bits of accumulation. The shifter performs logical and arith-
metic shifts, normalization, denormalization and derive
exponent operations. The shifter can be used to efficiently
implement numeric format control including multiword and
block floating-point representations.
The internal result (R) bus connects the computational units so
that the output of any unit may be the input of any unit on the
next cycle.
The ADSP-21xx family DSPs contain a shadow register that is
useful for single cycle context switching of the processor.
A powerful program sequencer and two dedicated data address
generators ensure efficient delivery of operands to these compu-
tational units. The sequencer supports conditional jumps, sub-
routine calls and returns in a single cycle. With internal loop
counters and loop stacks, the ADSP-2183 executes looped code
with zero overhead; no explicit jump instructions are required to
maintain loops.
Two data address generators (DAGs) provide addresses for
simultaneous dual operand fetches (from data memory and
program memory). Each DAG maintains and updates four
address pointers. Whenever the pointer is used to access data
(indirect addressing), it is post-modified by the value of one of
four possible modify registers. A length value may be associated
with each pointer to implement automatic modulo addressing
for circular buffers.
Efficient data transfer is achieved with the use of five internal
buses:
• Program Memory Address (PMA) Bus
• Program Memory Data (PMD) Bus
• Data Memory Address (DMA) Bus
• Data Memory Data (DMD) Bus
• Result (R) Bus
The two address buses (PMA and DMA) share a single external
address bus, allowing memory to be expanded off-chip, and the
two data buses (PMD and DMD) share a single external data
bus. Byte memory space and I/O memory space also share the
external buses.
Program memory can store both instructions and data, permit-
ting the ADSP-2183 to fetch two operands in a single cycle,
one from program memory and one from data memory. The
ADSP-2183 can fetch an operand from program memory and
the next instruction in the same cycle.
EZ-ICE and SoundPort are registered trademarks of Analog Devices, Inc.
