ADSP-2183
–19–
REV. C
Parameter Min Max Unit
IDMA Address Latch
Timing Requirements:
t
IALP
Duration of Address Latch
1, 2
10 ns
t
IASU
IAD15–0 Address Setup before Address Latch End
2
5ns
t
IAH
IAD15–0 Address Hold after Address Latch End
2
2ns
t
IKA
IACK Low before Start of Address Latch
1
0ns
t
IALS
Start of Write or Read after Address Latch End
2, 3
3ns
NOTES
1
Start of Address Latch = IS Low and IAL High.
2
End of Address Latch = IS High or IAL Low.
3
Start of Write or Read = IS Low and IWR Low or IRD Low.
t
IKA
IAD150
IACK
IAL
IS
IRD OR
IWR
t
IALP
t
IASU
t
IAH
t
IALS
Figure 14. IDMA Address Latch
ADSP-2183
–20– REV. C
Parameter Min Max Unit
IDMA Write, Short Write Cycle
Timing Requirements:
t
IKW
IACK Low before Start of Write
1
0ns
t
IWP
Duration of Write
1, 2
15 ns
t
IDSU
IAD15–0 Data Setup before End of Write
2, 3, 4
5ns
t
IDH
IAD15–0 Data Hold after End of Write
2, 3, 4
2ns
Switching Characteristic:
t
IKHW
Start of Write to IACK High 15 ns
NOTES
1
Start of Write = IS Low and IWR Low.
2
End of Write = IS High or IWR High.
3
If Write Pulse ends before IACK Low, use specifications t
IDSU
, t
IDH
.
4
If Write Pulse ends after IACK Low, use specifications t
IKSU
, t
IKH
.
IAD150
DATA
t
IKHW
t
IKW
t
IDSU
IACK
t
IWP
t
IDH
IS
IWR
Figure 15. IDMA Write, Short Write Cycle
ADSP-2183
–21–
REV. C
Parameter Min Max Unit
IDMA Write, Long Write Cycle
Timing Requirements:
t
IKW
IACK Low before Start of Write
1
0ns
t
IKSU
IAD15–0 Data Setup before IACK Low
2, 3
0.5t
CK
+ 10 ns
t
IKH
IAD15–0 Data Hold after IACK Low
2, 3
2ns
Switching Characteristics:
t
IKLW
Start of Write to IACK Low
4
1.5t
CK
ns
t
IKHW
Start of Write to IACK High 15 ns
NOTES
1
Start of Write = IS Low and IWR Low.
2
If Write Pulse ends before IACK Low, use specifications t
IDSU
, t
IDH
.
3
If Write Pulse ends after IACK Low, use specifications t
IKSU
, t
IKH
.
4
This is the earliest time for IACK Low from Start of Write. For IDMA Write Cycle relationships, please refer to the ADSP-21xx Family User’s Manual, Third Edition.
IAD150
DATA
t
IKHW
t
IKW
IACK
IS
IWR
t
IKLW
t
IKH
t
IKSU
Figure 16. IDMA Write, Long Write Cycle

ADSP-2183KCAZ-210

Mfr. #:
Manufacturer:
Analog Devices Inc.
Description:
Digital Signal Processors & Controllers - DSP, DSC 16B 52 MIPS 3.3V 2 Serial Prts Host Prt
Lifecycle:
New from this manufacturer.
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