LOW SKEW, 1-TO-16
LVCMOS/LVTTL CLOCK GENERATOR
87016 DATA SHEET
10 REVISION C 06/26/15
APPLICATION INFORMATION
FIGURE 1. SINGLE ENDED SIGNAL DRIVING DIFFERENTIAL INPUT
Figure 1 shows how the differential input can be wired to accept
single ended levels. The reference voltage V_REF = V
DD
/2 is
generated by the bias resistors R1, R2 and C1. This bias circuit
should be located as close as possible to the input pin. The ratio
WIRING THE DIFFERENTIAL INPUT TO ACCEPT SINGLE ENDED LEVELS
of R1 and R2 might need to be adjusted to position the V_REF
in the center of the input voltage swing. For example, if the input
clock swing is only 2.5V and V
DD
= 3.3V, V_REF should be 1.25V
and R2/R1 = 0.609.
INPUTS:
CLK INPUT:
For applications not requiring the use of a clock input, it can be
left fl oating. Though not required, but for additional protection, a
1kΩ resistor can be tied from the CLK input to ground.
CLK/nCLK I
NPUT:
For applications not requiring the use of the differential input,
both CLK and nCLK can be left fl oating. Though not required,
but for additional protection, a 1kΩ resistor can be tied from
CLK to ground.
LVCMOS C
ONTROL PINS:
All control pins have internal pull-ups or pull-downs; additional
resistance is not required but can be added for additional
protection. A 1kΩ resistor can be used.
RECOMMENDATIONS FOR UNUSED INPUT AND OUTPUT PINS
OUTPUTS:
LVCMOS OUTPUT:
All unused LVCMOS output can be left fl oating. We recommend
that there is no trace attached.
