REVISION C 06/26/15
87016 DATA SHEET
7 LOW SKEW, 1-TO-16
LVCMOS/LVTTL CLOCK GENERATOR
TABLE 5C. AC CHARACTERISTICS, V
DD
= 3.3V±5%, V
DDOX
= 1.8V±5%, TA = 0°C TO 85°C
Symbol Parameter Test Conditions Minimum Typical Maximum Units
f
MAX
Output Frequency 250 MHz
tp
LH
Propagation Delay,
Low to High
CLK0; NOTE 1A 3.1 3.8 4.5 ns
CLK1, nCLK1;
NOTE 1B
3.1 3.8 4.5 ns
tsk(b) Bank Skew; NOTE 2, 7 Measured on the Rising Edge 30 ps
tsk(o) Output Skew; NOTE 3, 7 Measured on the Rising Edge 170 ps
tsk(pp) Part-to-Part Skew; NOTE 5, 7 750 ps
t
R
/ t
F
Output Rise/Fall Time; NOTE 6 20% to 80% 200 700 ps
odc Output Duty Cycle
f < 175MHz 45 55 %
f ≥ 175MHz
40 60 %
t
EN
Output Enable Time; NOTE 6 10 ns
t
DIS
Output Disable Time; NOTE 6 10 ns
All parameters measured at 250MHz unless noted otherwise.
NOTE 1A: Measured from the V
DD
/2 of the input to V
DDOX
/2 of the output.
NOTE 1B: Measured from the differential input crossing point to V
DDOX
/2 of the output.
NOTE 2: Defi ned as skew within a bank with equal load conditions.
NOTE 3: Defi ned as skew between outputs at the same supply voltage and with equal load conditions.
Measured at V
DDOX
/2.
NOTE 4: Defi ned as skew across banks of outputs switching in the same direction operating at different frequencies
with the same supply voltages and equal load conditions. Measured at V
DDOX
/2.
NOTE 5: Defi ned as skew between outputs on different devices operating a the same supply voltages and with equal
load conditions. Using the same type of input on each device, the output is measured at V
DDOX
/2.
NOTE 6: These parameters are guaranteed by characterization. Not tested in production.
NOTE 7: This parameter is defi ned in accordance with JEDEC Standard 65.
