LOW SKEW, 1-TO-16
LVCMOS/LVTTL CLOCK GENERATOR
87016 DATA SHEET
4 REVISION C 06/26/15
TABLE 4A. POWER SUPPLY DC CHARACTERISTICS, V
DD
= 3.3V±5%, TA = 0°C TO 85°C
Symbol Parameter Test Conditions Minimum Typical Maximum Units
V
DD
Positive Supply Voltage 3.135 3.3 3.465 V
V
DDOx
Output Supply Voltage; NOTE 1
3.135 3.3 3.465 V
2.375 2.5 2.625 V
1.71 1.8 1.89 V
I
DD
Power Supply Current 100 mA
I
DDOx
Output Supply Current; NOTE 2 15 mA
NOTE 1: V
DDOx
denotes V
DDOA
, V
DDOB
, V
DDOC
, and V
DDOD
. NOTE 2: I
DDOx
denotes I
DDOA
, I
DDOB
, I
DDOC
, and I
DDOD
.
Symbol
Parameter Test Conditions Minimum Typical Maximum Units
V
IH
Input
High Voltage
DIV_SELA:DIV_SELD,
CLK_ENA:CLK_END,
nMR/OE, CLK_SEL
2V
DD
+ 0.3 V
CLK0
2V
DD
+ 0.3 V
V
IL
Input
Low Voltage
DIV_SELA:DIV_SELD,
CLK_ENA:CLK_END,
nMR/OE, CLK_SEL
-0.3 0.8 V
CLK0
-0.3 1.3 V
I
IH
Input
High Current
CLK_ENA:CLK_END,
DIV_SELA:DIV_SELD,
nMR/OE
V
DD
= V
IN
= 3.465V 5 µA
CLK0, CLK_SEL
V
DD
= V
IN
= 3.465V 150 µA
I
IL
Input
Low Current
CLK_ENA:CLK_END,
DIV_SELA:DIV_SELD,
nMR/OE
V
DD
= 3.465V, V
IN
= 0V -150 µA
CLK0, CLK_SEL
V
DD
= 3.465V, V
IN
= 0V -5 µA
V
OH
Output High Voltage; NOTE 1
V
DDOx
= 3.3V ± 5%; NOTE 2 2.6 V
V
DDOx
= 2.5V ± 5%; NOTE 2 1.8 V
V
DDOx
= 1.8V ± 5%; NOTE 2 I
OH
=
-2mA
V
DDOx
DD
- 0.45 V
V
OL
Output Low Voltage; NOTE 1
V
DDOx
= 3.3V ± 5%; NOTE 2 0.5 V
V
DDOx
= 2.5V ± 5%; NOTE 2 0.5 V
V
DDOx
= 1.8V ± 5%; NOTE 2 I
OL
=
2mA
0.45 V
I
OZL
Output Tristate Current Low
-5 µA
I
OZH
Output Tristate Current High
A
NOTE 1: Outputs terminated with 50W to V
DDOX
/2. See Parameter Measurement Information, Output Load Test Circuit.
NOTE 2: V
DDOx
denotes V
DDOA
, V
DDOB,
V
DDOC
and V
DDOD
.
TABLE 4B. LVCMOS/LVTTL DC CHARACTERISTICS, V
DD
= 3.3V±5%, TA = 0°C TO 85°C
ABSOLUTE MAXIMUM RATINGS
Supply Voltage, V
DD
4.6V
Inputs, V
I
-0.5V to V
DD
+ 0.5 V
Outputs, V
O
-0.5V to V
DDOx
+ 0.5V
Package Thermal Impedance, θ
JA
47.9°C/W (0 lfpm)
Storage Temperature, T
STG
-65°C to 150°C
NOTE: Stresses beyond those listed under Absolute
Maximum Ratings may cause permanent damage to the
device. These ratings are stress specifi cations only. Functional
operation of product at these conditions or any conditions
beyond those listed in the DC Characteristics or AC Charac-
teristics is not implied. Exposure to absolute maximum rating
conditions for extended periods may affect product reliability.
REVISION C 06/26/15
87016 DATA SHEET
5 LOW SKEW, 1-TO-16
LVCMOS/LVTTL CLOCK GENERATOR
TABLE 4C. DIFFERENTIAL DC CHARACTERISTICS, V
DD
= 3.3V±5%, TA = 0°C TO 85°C
Symbol Parameter
Test Conditions Minimum Typical Maximum Units
I
IH
Input High Current
nCLK1 V
IN
= V
DD
= 3.465V 5 µA
CLK1 V
IN
= V
DD
= 3.465V 150 µA
I
IL
Input Low Current
nCLK1 V
IN
= 0V, V
DD
= 3.465V -150 µA
CLK1 V
IN
= 0V, V
DD
= 3.465V -5 µA
V
PP
Peak-to-Peak Input Voltage 0.15 1.3 V
V
CMR
Common Mode Input Voltage;
NOTE 1, 2
GND + 0.5 V
DD
- 0.85 V
NOTE 1: For single ended applications, the maximum input voltage for CLK1, nCLK1 is V
DD
+ 0.3V.
NOTE 2: Common mode voltage is defi ned as V
IH
.
TABLE 5A. AC CHARACTERISTICS, V
DD
= V
DDOX
= 3.3V±5%, TA = 0°C TO 85°C
Symbol Parameter Test Conditions Minimum Typical Maximum Units
f
MAX
Output Frequency 250 MHz
tp
LH
Propagation Delay,
Low to High
CLK0; NOTE 1A 2.8 3.2 3.7 ns
CLK1, nCLK1;
NOTE 1B
2.9 3.4 3.9 ns
tsk(b) Bank Skew; NOTE 2, 7 Measured on the Rising Edge 30 ps
tsk(o) Output Skew; NOTE 3, 7 Measured on the Rising Edge 150 ps
tsk(pp) Part-to-Part Skew; NOTE 5, 7 750 ps
t
R
/ t
F
Output Rise/Fall Time; NOTE 6 20% to 80% 200 700 ps
odc Output Duty Cycle
f < 175MHz 45 55 %
f 175MHz
40 60 %
t
EN
Output Enable Time; NOTE 6 10 ns
t
DIS
Output Disable Time; NOTE 6 10 ns
All parameters measured at 250MHz unless noted otherwise.
NOTE 1A: Measured from the V
DD
/2 of the input to V
DDOX
/2 of the output.
NOTE 1B: Measured from the differential input crossing point to V
DDOX
/2 of the output.
NOTE 2: Defi ned as skew within a bank with equal load conditions.
NOTE 3: Defi ned as skew between outputs at the same supply voltage and with equal load conditions.
Measured at V
DDOX
/2.
NOTE 4: Defi ned as skew across banks of outputs switching in the same direction operating at different frequencies
with the same supply voltages and equal load conditions. Measured at V
DDOX
/2.
NOTE 5: Defi ned as skew between outputs on different devices operating a the same supply voltages and with equal
load conditions. Using the same type of input on each device, the output is measured at V
DDOX
/2.
NOTE 6: These parameters are guaranteed by characterization. Not tested in production.
NOTE 7: This parameter is defi ned in accordance with JEDEC Standard 65.
LOW SKEW, 1-TO-16
LVCMOS/LVTTL CLOCK GENERATOR
87016 DATA SHEET
6 REVISION C 06/26/15
TABLE 5B. AC CHARACTERISTICS, V
DD
= 3.3V±5%, V
DDOX
= 2.5V±5%, TA = 0°C TO 85°C
Symbol Parameter Test Conditions Minimum Typical Maximum Units
f
MAX
Output Frequency 250 MHz
tp
LH
Propagation Delay,
Low to High
CLK0; NOTE 1A 2.9 3.3 3.8 ns
CLK1, nCLK1;
NOTE 1B
3 3.5 4 ns
tsk(b) Bank Skew; NOTE 2, 7 Measured on the Rising Edge 30 ps
tsk(o) Output Skew; NOTE 3, 7 Measured on the Rising Edge 160 ps
tsk(pp) Part-to-Part Skew; NOTE 5, 7 750 ps
t
R
/ t
F
Output Rise/Fall Time; NOTE 6 20% to 80% 200 700 ps
odc Output Duty Cycle
f < 175MHz 45 55 %
f
≥≥ 175MHz
40 60 %
t
EN
Output Enable Time; NOTE 6 10 ns
t
DIS
Output Disable Time; NOTE 6 10 ns
All parameters measured at 250MHz unless noted otherwise.
NOTE 1A: Measured from the V
DD
/2 of the input to V
DDOX
/2 of the output.
NOTE 1B: Measured from the differential input crossing point to V
DDOX
/2 of the output.
NOTE 2: Defi ned as skew within a bank with equal load conditions.
NOTE 3: Defi ned as skew between outputs at the same supply voltage and with equal load conditions.
Measured at V
DDOX
/2.
NOTE 4: Defi ned as skew across banks of outputs switching in the same direction operating at different frequencies
with the same supply voltages and equal load conditions. Measured at V
DDOX
/2.
NOTE 5: Defi ned as skew between outputs on different devices operating a the same supply voltages and with equal
load conditions. Using the same type of input on each device, the output is measured at V
DDOX
/2.
NOTE 6: These parameters are guaranteed by characterization. Not tested in production.
NOTE 7: This parameter is defi ned in accordance with JEDEC Standard 65.

87016AYLF

Mfr. #:
Manufacturer:
IDT
Description:
Clock Generators & Support Products 16 LVCMOS OUT BUFFER/DIVIDER
Lifecycle:
New from this manufacturer.
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