2
SAM9M10 [SUMMARY]
6355ES–ATARM–12-Mar-13
1. Features
• 400 MHz ARM926EJ-S™ ARM® Thumb® Processor
–32 KBytes Data Cache, 32 KBytes Instruction Cache, MMU
• Memories
– DDR2 Controller 4-bank DDR2/LPDDR, SDRAM/LPSDR
– External Bus Interface supporting 4-bank DDR2/LPDDR, SDRAM/LPSDR, Static Memories, CompactFlash
®
, SLC NAND
Flash with ECC
– One 64-KByte internal SRAM, single-cycle access at system speed or processor speed through TCM interface
– One 64-KByte internal ROM, embedding bootstrap routine
• Peripherals
– Multi-format Video Decoder
– LCD Controller supporting STN and TFT displays up to 1280*860
– ITU-R BT. 601/656 Image Sensor Interface
– USB Device High Speed, USB Host High Speed and USB Host Full Speed with On-Chip Transceiver
– 10/100 Mbps Ethernet MAC Controller
–Two High Speed Memory Card Hosts (SDIO, SDCard, MMC)
– AC'97 controller
–Two Master/Slave Serial Peripheral Interfaces
–Tw
o Three-channel 16-bit Timer/Counters
–Two Synchronous Serial Controllers (I2S mode)
– Four-channel 16-bit PWM Controller
–Two Two-wire Interfaces
– Four USARTs with ISO7816, IrDA, Manchester and SPI modes, one DBGU
– 8-channel 10-bit ADC with 4-wire Touch Screen support
• System
– 133 MHz twelve 32-bit layer AHB Bus Matrix
–37 DMA Channels
– Boot from NAND Flash, SDCard, DataFlash® or serial DataFlash
– Reset Controller with on-chip Power-on Reset
– Selectable 32768 Hz Low-power and 12 MHz Crystal Oscillators
– Internal Low-power 32 kHz RC Oscillator
– One PLL for the system and one 480 MHz PLL optimized for USB High Speed
–Tw
o Programmable External Clock Signals
– Advanced Interrupt Controller and Debug Unit
– Periodic Interval Timer, Watchdog Timer, Real Time Timer and Real Time Clock
• I/O
– Five 32-bit Parallel Input/Output Controllers
– 160 Programmable I/O Lines Multiplexed with up to Two Peripheral I/Os with Schmitt trigger input
• Package
– 324-ball TFBGA, pitch 0.8 mm
