LTC4229
16
4229f
For more information www.linear.com/LTC4229
applicaTions inForMaTion
comparator drives high when the FB pin rises above
1.235V, and drives low when FB falls below 1.215V. The
power good status for the input supply is reported via an
open-drain output, PWRGD. It is normally pulled high by
an external pull-up resistor or the internal 10µA pull-up.
The PWRGD pin pulls low when the FB power good com
-
parator is high and the HGATE drive exceeds 4.2V. The
PWRGD pin goes high when the HGATE is turned off by the
UV, OV or EN pins, or when the FB power good comparator
drives low, or when INTV
CC
enters undervoltage lockout.
CPO and DGATE Start-Up
In applications where a single ideal diode MOSFET is placed
on the supply side, CPO is initially pulled up to a diode
below the DSRC pin when first powered up (see Figure
13). In back-to-back MOSFETs applications, CPO starts
off at 0V, since DSRC is near ground (see Figure14). CPO
starts ramping up 7µs after INTV
CC
clears its undervolt-
age lockout level. Another 40µs later, DGATE also starts
ramping
up with CPO. The CPO ramp rate is determined
by the CPO pull-up current into the combined
CPO and
DGA
TE pin capacitances. An internal clamp limits the
CPO pin voltage to 12V above the DSRC pin, while the
final DGATE pin voltage is determined by the gate drive
amplifier. An internal 12V clamp limits the DGATE pin
voltage above DSRC.
CPO Capacitor Selection
The recommended value of the capacitor between the CPO
and DSRC pins is approximately 10× the input capacitance
C
ISS
of the ideal diode MOSFET. A larger capacitor takes a
correspondingly longer time to charge up by the internal
charge pump. A smaller capacitor suffers more voltage
drop during a fast gate turn-on event as it shares charge
with the MOSFET gate capacitance.
MOSFET Selection
The LTC4229 drives N-channel MOSFETs to conduct the
load current. The important features of the MOSFETs are
on-resistance R
DS(ON)
, the maximum drain-source voltage
BV
DSS
and the threshold voltage.
The gate drive for the ideal diode and Hot Swap MOSFET is
guaranteed to be greater than 5V when the supply voltage
at IN is between 2.9V and 7V. When the supply voltage
at IN is greater than 7V, the gate drive is guaranteed to
be greater than 10V. The gate drive is limited to 14V
. An
external
Zener diode can be used to clamp the potential
from the MOSFET’s gate to source if the rated breakdown
voltage is less than 14V.
The maximum allowable drain-source voltage BV
DSS
must be higher than the supply voltage including supply
transients as the full supply voltage can appear across the
MOSFET. If an input or output is connected to ground, the
full supply voltage will appear across the MOSFET. The
R
DS(ON)
should be small enough to conduct the maximum
load current, and also stay within the MOSFET’s power
rating.
Supply Transient Protection
When the capacitances at the input and output are very
small, rapid changes in current during input or output
short-circuit events can cause transients that exceed the
24V absolute maximum ratings of the IN and OUT pins.
To minimize such spikes, use wider traces or heavier
trace plating to reduce the power trace inductance. Also,
bypass locally with a 10µF electrolytic and 0.1µF ceramic,
or alternatively clamp the input with a transient voltage
suppressor Z1. A 100Ω, 0.1µF snubber damps the response
and eliminates ringing (see Figure 13).
Design Example
As a design example for selecting components, consider
a 12V system with a
7.6A maximum
load current for the
input supply (see Figure 1).
First, select the appropriate value of the current sense
resistor R
S
for the 12V supply. Calculate the sense resistor
value based on the maximum load current I
LOAD(MAX)
and
the lower limit for the current limit sense voltage threshold
∆V
SENSE(TH)(MIN)
.
R
S
=
Δ
SENSE(TH)(MIN)
I
LOAD(MAX)
=
22.5mV
7.6A
= 2.9mΩ
Choose a 2.5mΩ sense resistor with a 1% tolerance.
Next, calculate the R
DS(ON)
of the ideal diode MOSFET
to achieve the desired forward drop at maximum load.
