Technical Note
10/13
www.rohm.com
2011.05 - Rev.B
© 2011 ROHM Co., Ltd. All rights reserved.
BD95830MUV
I/O Equivalent Circuits
EN1, EN2 V
INS VREG
VCC FB1, FB2 VOUT1, VOUT2
VIN1, VIN2 BOOT1, BOOT2 SW1, SW2
VREG
50kΩ 500kΩ
500kΩ
BOOT
VINS
SW
BOOT
VIN
VREG
SW
VREG
Technical Note
11/13
www.rohm.com
2011.05 - Rev.B
© 2011 ROHM Co., Ltd. All rights reserved.
BD95830MUV
Notes for use
(1) Absolute Maximum Ratings
Use of the IC in excess of absolute maximum ratings (such as the input voltage or operating temperature range) may
result in damage to the IC. Assumptions should not be made regarding the state of the IC (e.g., short mode or open
mode) when such damage is suffered. If operational values are expected to exceed the maximum ratings for the device,
consider adding protective circuitry (such as fuses) to eliminate the risk of damaging the IC.
(2) Power Supply Polarity
Connecting the power supply in reverse polarity can cause damage to the IC. Take precautions when connecting the
power supply lines. An external power diode can be added.
(3) Power Supply Lines
In order to minimize noise, PCB layout should be designed such that separate, low-impedance power lines are routed to
the digital and analog blocks. Additionally, a coupling capacitor should be inserted between all power input pins and the
ground terminal. If electrolytic capacitors are used, keep in mind that their capacitance characteristics are reduced at
low temperatures.
(4) GND voltage
The potential of the GND pin must be the minimum potential in the system in all operating conditions.
(5) Thermal design
Use a thermal design that allows for a sufficient margin for power dissipation (Pd) under actual operating conditions.
(6) Inter-pin Shorts and Mounting Errors
Use caution when orienting and positioning the IC for mounting on printed circuit boards. Improper mounting may result
in damage to the IC. Shorts between output pins or between output pins and the power supply and GND pins caused by
poor soldering or foreign objects may result in damage to the IC.
(7) Operation in Strong Electromagnetic Fields
Using this product in strong electromagnetic fields may cause IC malfunction. Caution should be exercised in
applications where strong electromagnetic fields may be present.
(8) ASO - Area of Safe Operation
When using the IC, ensure that operating conditions do not exceed absolute maximum ratings or ASO of the output
transistors.
(9) Thermal shutdown (TSD) circuit
The IC incorporates a built-in thermal shutdown circuit, which is designed to turn the IC off completely in the event of
thermal overload. It is not designed to protect the IC from damage or guarantee its operation. ICs should not be used
after this function has activated, or in applications where the operation of this circuit is assumed.
TSD ON Temp. [] (typ.) Hysteresis Temp. [] (typ.)
BD95830MUV 175 15
(10) Testing on application boards
When testing the IC on an application board, connecting a capacitor directly to a low-impedance pin may subject the IC
to stress. Always discharge capacitors completely after each process or step. The IC’s power supply should always be
turned off completely before connecting or removing it from a jig or fixture during the evaluation process. To prevent
damage from static discharge, ground the IC during assembly and use similar precautions during transport and storage.
Technical Note
12/13
www.rohm.com
2011.05 - Rev.B
© 2011 ROHM Co., Ltd. All rights reserved.
BD95830MUV
(11) Regarding input pins of the IC
This monolithic IC contains P+ isolation and P substrate layers between adjacent elements in order to keep them
isolated. PN junctions are formed at the intersection of these P layers with the N layers of other elements, creating
parasitic diodes and/or transistors. For example (refer to the figure below):
When GND > Pin A and GND > Pin B, the PN junction operates as a parasitic diode
When GND > Pin B, the PN junction operates as a parasitic transistor
Parasitic diodes occur inevitably in the structure of the IC, and the operation of these parasitic diodes can result in
mutual interference among circuits, operational faults, or physical damage. Accordingly, conditions that cause these
diodes to operate, such as applying a voltage lower than the GND voltage to an input pin (and thus to the P substrate)
should be avoided.
(12) Ground Wiring Pattern
When using both small-signal and large-current GND traces, the two ground traces should be routed separately but
connected to a single ground potential within the application in order to avoid variations in the small-signal ground
caused by large currents. Also ensure that the GND traces of external components do not cause variations on GND
voltage.
Power Dissipation (VQFN032V5050)
IC Only
θ
j-a=328.9/W
IC mounted on 1-layer board (with 20.2 mm
2
copper thermal pad)
θj-a=142.0/W
IC mounted on 4-layer board (with 20.2 mm
2
pad on top layer,
5502 mm
2
pad on layers 2,3)
θj-a=38.3/W
IC mounted on 4-layer board (with 5505mm
2
pad on all layers)
θ
j-a=27.4/W
Example of IC structure
5.5
0 20 40 60 80 100 120
0
3.5
3.0
2.5
2.0
1.5
4.0
0.38W
0.88W
Power dissipation:Pd [W]
Ambient temperature :Ta []
1.0
0.5
4.5
5.0
3.26W
4.56W
140
Resistor Transistor (NPN)
N
N N
P
+
P
+
P
P substrate
GND
Parasitic element
Pin A
N
N
P
+
P
+
P
P substrate
GND
Parasitic element
Pin B
C
B
E
N
GND
Pin A
Parasitic
element
Pin B
Other adjacent elements
E
B C
GND
Parasitic
element

BD95830MUV-E2

Mfr. #:
Manufacturer:
Description:
Switching Voltage Regulators IC Pwr Swtch Reg Integrated FET
Lifecycle:
New from this manufacturer.
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